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LOSTCIRCUITS

SHORTCUTS:
Top page
Realigning the Focus
The Bumpy Road to DDR400
The SPD Fiasco
The Candidates
Test Beds and Methods
SPD Readouts
2:2:2-6 Performance
2:3:2-6 Performance
Relaxed Latencies
Conclusions

Your Comments?

 DDR400   
The New Platform
(Review by MS, May 6, 2003)


Stability results

We tested all modules at manual 2:2:2-6 settings with the DDR voltage set to 2.65V which in real live gave us a voltage reading of 2.68V. As it turned out, this is the lowest voltage that the P4C800 supplies, the 2.55V setting is broken and the Auto setting also supplies 2.68V. This is still within specs, there is nothing to worry about but it is necessary to have the complete system disclosure. Another issue we already mentioned in the review of the ASUS P4C800 is that the 200 MHz FSB setting results in 202 MHz, so does the 201 MHz and the 202 MHz, in other words, there is a faked granularity of bus speed settings without a real counterpart.


Highest stable frequency at which each pair of module was running. In some ways, it is no surprise that the Samsung and the KINGMAX fail at 2:2:2 latency settings at 202 MHz clock rate, the parts are labeled as CAS-3, even though the KINGMAX SPD reads them as CL2.5 modules.

Juicing Things Up: 2.75V

We increased the voltage to 2.75V (2.78V measured at the DIMM slots) to see what changes we would see:

Highest stable frequency at which each pair of module was running. The Samsung and KingMax still fail but that is no surprise. Otherwise, some modules get faster, some don't.

Earlier in this review, we pointed out that the Row-to-Column delay has become the most critical factor in DDR technology. Let's see what happens if we increase tRCD from 2 to 3 cycles.

next page:    => tRCD=3T =>

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