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Power Issues

One huge problem with current DDR is power consumption. A desktop system featuring 4 GB of DDR will consume on every read some 35-40 W of memory power. Reducing the nominal operating voltage from 2.5V to 1.8V, will result in power savings of 28 %. At the same time, a reduced voltage swing allows higher frequencies.

Unfortunately, it is not that easy. It is true that lower voltage swings enable higher frequencies but after a certain point, the ramping of the voltages will show a significant skew. The skew can be reduced by increased drive strength, however, with the drawback of a voltage overshoot / undershoot at the rising and falling edges, respectively. One additional problem with high frequency signalling is the phenomenon of trace delays. The solution in DDR was to add clock forwarding in form of a simple data strobe. DDR II takes things further by introducing a bidirectional, differential I/O buffer strobe consisting of DQS and /DQS as pull-up and pull-down signals. Differential means that the two signals are measured against each other instead of using a simple strobe signal and a reference point. In theory the pull-up and pull-down signals should be mirror-symmetric to each other but reality shows otherwise. That means that there will be skew-induced delays to reaching the output high and low voltages (VOH and VOL) and the cross points between DQS and /DQS used for clock forwarding will not necessarily coincide with the DQ crossing the reference voltage (Vref) or even be consistent from one clock to the next. The mismatch between clock and data reference points is referred to as the DQ-DQS skew.

Clock-Forwarding and OCD-calibration

DQS and DQ traces will never be a perfect square function, the slope of the voltage ramp relative to the clock cycle time will get shallower with increasing frequency. Increasing the signal strength results in voltage over- and undershoots. For simplicity reasons, we have drawn only one "real life" strobe signal and substituted simplified traces for the remaining signals. Simplified traces means that we use the point where the voltage reaches the High or Low Output enable threshold. Disregarding all jittter, in the upper part of the figure, DQS and /DQS are still unequal which results in shifting of their cross point. Since the cross point defines the source synchronous clocking or forwarded clock boundary, a mismatch between the external clock and the data clock will occur. This mismatch is the DQ-DQS skew which causes deterioration of the data integrity.

The lower half of the figure shows the hypothetical result of OCD calibration where all signals are matching perfectly. Every marketing person would give their first born for real traces as clean as those shown here, though.

In addition, while the input impedances of most I/O buffers on a single chip are usually in the same order, there can be slight differences between the individual DQs that make it difficult to find the all-encompassing formula. If different designs from different vendors have to be taken into account, the situation gets far more difficult.

One way to solve the problem is to use Off-Chip Driver calibration (OCD calibration) where both parts of the differential strobes are calibrated against each other and against the DQ signal. Through this sort of calibration, the ramping voltages are optimized for the buffer impedances to reduce over and undershooting at the rising and falling edges. More importantly, DQS and /DQS are matched so that their cross point coincides with the DQ signal crossing the reference voltage to eliminate DQ-DQS skew. In summary, the entire scheme results in better compatibility between different designs, higher signal integrity through minimization of DQ-DQS skew and reduced overshoot / undershoot for better signal quality.

BGA vs. TSOP

Probably the most overhyped and mis-interpreted aspect of DDR II is the migration from TSOP to a BGA interface with the argument that the little TSOP feet have too much resistance and inductivity / impedance and that the BGA interface will solve these problems. Keep in mind that the caliber of the TSOP feet is still orders of magnitude larger than the PCB traces. Keep in mind further that the package contacts still have to connect via bond wires to the actual pads on the die. Bond wires are typically 30 µm in diameter and compared to their resistance / impedance, the question of TSOP vs BGA becomes almost non-existent.

That does not mean that BGA has no advantages, on the contrary. However, the advantages are in the better control of signal integrity and easier calibration. Suffice it to say that with a standard design of DDR I without OCD-calibration, the benefit of BGA packaging is borderline measurable. However, it appears as if BGA is a prerequisite for OCD-calibration.

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