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Backward Compatibility

Depending on who is talking, DDR II will be either compatible or incompatible with DDR I. To make it short, compatibility is limited to the basic command set, that is, the codes for read, write or similar commands have not been altered. Likewise, the basic device timings remain the same. However, this is as far as compatibility goes, meaning that aside from hypothetically understanding the same commands, there is no practical compatibility.

As we mentioned on the first page of this review, DDR II DIMMs will feature 240 pins instead of 184 pins in DDR I, also, there are new functions that are not supported in DDR I but without which DDR II devices will not function (ODT, OCD-calibration, Posted CAS and AL, variable write latency). Moreover, the voltage interface is different, 1.8V will not drive a 2.5V DIMM and vice versa it might become a substitute for a cold cathode case lighting. Briefly, that is.

All Key Features At One Glance

* Megabit/pin/sec
** The original BL was defined as 4 QW, however, a burst of 8 QW has been added as far as we know per request of Intel/Samsung.
*** DDR I only uses a single DQS, using the cross point with the reference voltage. DDR II uses a differential DQS as shown on page 3.
+ CAS-3 is possible using a 533 MHz CAS-4 speed bin in DDR400 mode.
++ All current DDR I components are running at 1.8V internally, using voltage regulators to reduce VDD from 2.5V to 1.8V.
+++ Additive Latency can be 0,1,2,3,4T, the actual Read Latency is the sum of CAS latency and Additive Latency, e.g. CAS-4 + AL-4 =8T Read Latency.

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