LOSTCIRCUITS |
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DIMM'S and DIMM's
FAQ's and such
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(Review by MS)
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DIMMs:
Do I need to buy 12 ns DIMMs for older machines?
There are still lots of 12 ns DIMMs out there
and I am always amazed when they are being recommended by the sales people
with the argument that the older computer cannot handle 10 ns and therefore
they must buy 12 ns DIMMs. IMHO this is just a sales trick to get rid of
the older / lower quality stuff.
What is the difference between ..x64 and ..x72 DIMMs?
..x64 DIMMs are standard non parity while ..x72
DIMMs utilize additional 8 bits of memory bandwidth for Error Correction
Code (ECC) which is similar to parity. In contrast to conventional parity,
however, ECC does not result in a penalty cycle during normal read, only
when a 1 bit error occurs (which is the maximum, ECC is capable of correcting),
the correction results in a penalty cycle. ECC DIMMs can be run in a motherboard
that doesn't support ECC, in this case, the additional 8 bits will be ignored.
What is ECC?
Error correction code is a feature that enables
the system to correct memory errors of one bit. If ECC is enabled in the
BIOS, ECC memory is required to operate the system. ECC is restricted to
DIMMs and is recognized by the "..x72" label. The main difference between
ECC and the older "parity" memory is that in normal use, ECC is not slower
than non-ECC memory, an additional penalty cycle occurs only upon encountering
an error. For most PCs, the use of ECC is not really necessary, since the
occurrence of 1 bit memory errors is either not crucial or to seldom (if
something goes wrong, it is often more than one bit), however, for file
servers, ECC is a valuable addition because, otherwise, even small
errors are propagated downstream and can cause massive operating failure
in the client machines.
What is the function of the EEPROM?
The EEPROM is a little chip (electrically erasable
programmed read only memory) the function of which is to interact with
the BIOS in order to coordinate the memory timing. While this does not
really influence the timing settings e.g. 2-1-1-1 versus 3-1-1-1, it helps
to achieve greater precision in the memory transfer between the main memory
and the L2 cache. In other words, if the data transfer occurs at exactly
the time when the L2 cache is ready to receive, it results in less errors
than if two independent systems are told to run at the same frequency but
they may be offset from each other by a tad. The routine that performs
this sharpening or coordinating of memory timing is called Serial Presence
Detect (SPD). If a specific motherboard/ chipset does not support SPD,
it is ignored without negative side effects.
What does SPD mean?
SPD stands for serial presence detect which basically
means an interaction between the main memory and the L2 cache in order
to coordinate the memory timing (data transfer frequency; see "EEPROM"
above).
Can 10 ns DIMMs be PC-100 compliant?
Yes, most 10ns DIMMs actually use memory chips
that are capable of handling 7 or 8 ns, particularly older (meaning
a few months) DIMMs are labeled 10 ns because people were afraid that their
slower boards couldn't handle the higher memory timing. PC 100 compliant
basically means that the board and layout of the DIMMs follows the Intel
PC 100 specifications. One, maybe not real pitfall of the PC 100 compliance
is the integration of specific ground loops and echo suppressors in the
board which are optimized for frequencies of multiples of 33 MHz, that
is 66, 100 and 133MHz. I have heard of a few cases where these DIMMs were
running clean at 66 (33x2) 83 (33x2.5) and 100 (33x3) MHz but crashed at
second harmonic frequencies e.g. 75 (33x2.25) MHz. It must be said, though
that those were isolated events, still, it is noteworthy.
Can 10 ns DIMMs be faster than 8 ns DIMMs?
Yes, 10ns DIMMs can be faster because of
a faster CAS (column access strobe). At present, there are 10 ns DIMMs
out that have a CAS delay of 2 cycles whereas 8 ns DIMMs still cannot go
below a 3 cycle penalty. What that means is quite simply that the delay
in access is 10 ns x 2 = 20 ns for the 10 ns DIMMs whereas the access delay
for the 8 ns DIMMs is 8 ns x 3 = 24 ns ergo slower. Of course there are
numerous 10 ns DIMMs with a CAS delay of 3 which then, naturally are slower
than the 8 ns modules.
What is the difference between CAS-2 and CAS-3 DIMMs
You have to think of a DIMM or a memory chip
as a spreadsheet in which the different bits of information are stored
temporarily in columns and rows. The access pattern ot strobe follows this
organization in that first a field within the first column is accessed
and subsequently all other adresses within this row can be read without
additional penalty cycles. However since the information is spread through
several rows of data fields, the strobe has to access the column again
to move down to the next row. This column access usually involves 2 or
3 penalty cycles which are added to the normal access cycle therefore you
see a Column Access Strobe (CAS) delay of 2 (1 normal + 2 penalty) or 3
(1 normal + 3 penalty cycles). Needless to say that CAS-2 is quite a bit
faster than CAS-3.
One has to keep in mind though that CAS-2 and
CAS-3 are not hardwired into the DIMMs. However, in the current parlance,
a PC-100 CAS-2 DIMM refers to a DIMM that is capable of handling the 100
MHz speed at a CAS latency of 2 (two penalty cycles). At higher bus speeds,
these DIMMs often have to be accessed at less aggressive timing settings,
e.g. @ 124 MHz a DIMM that can run at 100 MHz at CAS-2 will most likely
have to be set up as CAS-3). BTW, PC-100 CAS-2 memory is often also called
BX memory because the BX chipset was the first to exceed the 100 MHz barrier
and thus the limitations of the older DIMMs that already needed 3 penalty
cycles (CAS-3) at 100 MHz or below. In a few months this whole field will
change dramatically with the introduction of ESDRAM (a preview is below,
the full article is under construction).
What are the fastest DIMMs currently available
The fastest DIMMs that are actually still in
the experimental stage are using so called low latency memory chips and
go by the name ESDRAM. According to the manufacturer's (Enhanced
Memory Systems) specifications, the new modules that will hit the market
in Q4 1998 will be fully compatible with current DIMM slot architecture
and be capable of handling up to 166 MHz (darn, I wish they would send
me a test sample :-) )
Manufacturer links:
For those who take this page as an entry-level crash course about memory but would
like further readings, I recommend the following websites:
next page: => previous Dimm FAQs =>
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