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Inside the EDDR Chip
Combining DRAM storage and SRAM speed
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(Review by MS, November 27, 2000)
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Zooming in
Data are stored within the array of memory cells lying under the grid array of red (column select) and blue (row select) lines. In order to access the data, first an x-coordinate is selected (row address) and the row is activated. After the row is activated which means that the data are latched into sense amplifiers (see below), a read command can be issued which selects a column, and sets it high. At the point where the two lines (row and column) cross, the data are latched onto data lines and move towards the outside of the array to be further amplified by secondary sense amps (a common but not mandatory feature, though).
Schematic diagram of the processes involved in selecting data from within the DRAM array. On the left half, a bank activate command has been issued and the row decoder has selected one row (keep in mind that, in this case, according to the DRAM terminology, rows are what usually would be columns and vice versa). After the RAS-To-CAS delay, a read command is issued, upon which the CAS selects one specific column. The point in the array where the two lines meet is the correct memory address.
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