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Zooming in more

Ok, now we are at the point where the data have been selected but we still need to get them out of the array into the output buffers. In other words, we need data lines in addition to the row and column select lines. In most cases, the data lines are running in parallel to the row select lines. For simplicity reasons, however, we assume that the data lines will be running horizontal in parallel with the column (y) select lines.

Most designs nowadays use interleaved arrays of primary sense amplifiers (1.SA) and memory cells (lighter grey). Each bi-directional black arrow represents a pair of bit lines projecting from the 1.SA either to the left or the right into the memory cell array. As a result of this architecture memory cells talk to sense amps on either flank, vice versa, it is the same situation since sense amps are talking to memory cells on either side. For a better distribution of power and heat, current solutions often use 2 hemi-rows as shown above to access the data from the memory cells sandwiched in between. Red lines are the row seloct lines, column select lines are dark green and data lines are turquoise. The secondary sense amps and global data lines are purple.

Once again, from a function perspective: One row or two hemi-rows are activated and the data are latched through the bitlines into the primary sense amps. After the RAS-to-CAS delay (specified in the BIOS to warrant completion of this process), a read command is issued which is decoded in the column decoder (green) and causes the signal to travel through the column select line into the array. When Row and Column select signals meet, the data are latched onto the data lines (turquoise) and travel out of the array to the secondary sense amps. There they are amplified again and sent via global data lines into the output buffers. All processes from the point of where the read command is issued until the data are output need to be completed within the time interval allocated for the CAS latency. This means, column decoding, sending the signal into the array, latching the data on the data lines, getting them back out to the secondary sense amps and finally moving them to the output pins, all are part of the CAS latency.

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