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| Inside the EDDR Chip Combining DRAM storage and SRAM speed | |
| (Review by MS, November 27, 2000) |
Some Real Examples
Didn't you always want to see what a memory chip looks like on the inside? Here are a few snapshots. The procedure is quite simple, you take a chip off the DIMM, etch off the top layer with hydrofluoride and clean it up a bit. Then you put the chip under a microscope and ... voila! Unfortunately, this process is irreversible.
A low power magnification picture of a DDR chip stripped of its packaging, exposing the top traces (metal layer 2), in this case the column select lines and the global data lines. The zigzag lines are the areas of contact with the primary sense amplifiers, the areas in between contain the DRAM cells (capacitors) and the bitlines including the transistor-based pass gates.

High power magnification of the column select lines and the contacts to the primary sense amps. In parallel to the column select lines run thicker power lines to the sense amps. Picture taken with differential interference contrast (Nomarski) optics.

After another bath in hydrofluoride, the metal layers are etched away and the actual array including the sense amps is exposed. The "height" of the sense amps (usually one would call it width) is 41 µm to give an idea about the dimensions here. The width of the sense amps, for reference, is the number of memory cells it is connected to.
Signal propagation along traces has, historically, been a negligible factor within the timing schematics, however, with increasing clock and data rates, these processes take up an increasingly important part of the entire timing sequence. A rough estimate is that each one-way transaction can take up to 1 ns, consequently, the total trace delay (without latching) can take as much as 2 ns. Although this still appears minimal, one needs to keep in mind that the clock cycle time (tCK) will be no more than 5 ns as soon as 200 MHz clock rate becomes an option. Therefore, shaving off 2 ns from an 11.5 ns CAS delay to complete the entire process within 9.5 ns would allow the move from a CAS 3 or 2.5 part (SDRAM or DDR, respectively) to a true CAS-2 part.
next page: => Meet EDDR! =>
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