Navigate:

Advice
Beginners
BIOS Guide
CPUs
Links
Mainboards
Memory
Network
Storage
Video/Sound Cards

Contact
Forum
SiteMap
Sponsors
WebNews
Home

. .


CPU
Intel
P4 840 D
P4 820 D
P4 630
P4 640
P4 650
P4 660
P4 670

AMD
Athlon64
3500+
3700+
3800+
4000+
X2-3800+
X2-4200+
X2-4400+
X2-4600+
X2-4800+

1-Way Opteron
Opteron 144
Opteron 146
Opteron 148
Opteron 150
Opteron 152

2-Way Opteron
Opteron 240
Opteron 242
Opteron 244
Opteron 246
Opteron 248
Opteron 250
Opteron 252

2-Way Dual Core Opteron
Opteron 270
Opteron 275

nVidia
GF 7800GT
GF 6800GT
GF 6600GT

ATI
R X850 XT PE
R X850 XT
R X800 XT PE
R X800 XT
R X800 XL

Memory

Corsair
Crucial
Kingston
Mushkin
OCZ

What are you
shopping for?







































































LOSTCIRCUITS

SHORTCUTS:
Top page
(DDR)-SDRAM chip overview
Row and Column select
the devil in the traces
Photo Gallery
Functional anatomy of EDDR
Cache and Power Saving
Changing the Commands - Conclusion
 Inside the EDDR Chip   
Combining DRAM storage and SRAM speed
(Review by MS, November 27, 2000)


Some Real Examples

Didn't you always want to see what a memory chip looks like on the inside? Here are a few snapshots. The procedure is quite simple, you take a chip off the DIMM, etch off the top layer with hydrofluoride and clean it up a bit. Then you put the chip under a microscope and ... voila! Unfortunately, this process is irreversible.


A low power magnification picture of a DDR chip stripped of its packaging, exposing the top traces (metal layer 2), in this case the column select lines and the global data lines. The zigzag lines are the areas of contact with the primary sense amplifiers, the areas in between contain the DRAM cells (capacitors) and the bitlines including the transistor-based pass gates.

High power magnification of the column select lines and the contacts to the primary sense amps. In parallel to the column select lines run thicker power lines to the sense amps. Picture taken with differential interference contrast (Nomarski) optics.

After another bath in hydrofluoride, the metal layers are etched away and the actual array including the sense amps is exposed. The "height" of the sense amps (usually one would call it width) is 41 µm to give an idea about the dimensions here. The width of the sense amps, for reference, is the number of memory cells it is connected to.

Signal propagation along traces has, historically, been a negligible factor within the timing schematics, however, with increasing clock and data rates, these processes take up an increasingly important part of the entire timing sequence. A rough estimate is that each one-way transaction can take up to 1 ns, consequently, the total trace delay (without latching) can take as much as 2 ns. Although this still appears minimal, one needs to keep in mind that the clock cycle time (tCK) will be no more than 5 ns as soon as 200 MHz clock rate becomes an option. Therefore, shaving off 2 ns from an 11.5 ns CAS delay to complete the entire process within 9.5 ns would allow the move from a CAS 3 or 2.5 part (SDRAM or DDR, respectively) to a true CAS-2 part.

next page:    => Meet EDDR! =>

Click Here!

If you enjoyed reading this article and found it useful, please consider making a small donation to LostCircuits.
Thank you!

General disclaimer: This page only reflects the author's personal opinion and assumes no responsibility whatsoever regarding any of the contents or any damages that may occur explicitly or implicitly from reading the contents of this site. All names and trademarks mentioned in this review are the exclusive property of the respective parent companies.
All contents of this site are protected by international copyright laws. Reproduction of the contents even in parts is not allowed except after written permission by the author and referral to this site.
Copyright 1998 - 2007 LostCircuits