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Time to look at something new:

Above I mentioned the hybrid architecture of EDDR, which proposes an embedded SRAM cells as a substitute for the secondary sense amps. Before going into the functional details, lets take a look at the design principles underlying this new architecture:

Overview of the EDDR architecture: The most noticeable difference between the proposed EDDR and a conventional design as shown above is that there are no more column select lines going into the array. The secondary sense amps have been replaced by a direct mapped 8 kbit SRAM row cache. Address selection on the level of column addresses is done by a column decoder accessing the individual addresses within the row cache. Since unwanted feedback to the DRAM array is eliminated almost completely, the read (data out) path can carry a stronger signal at higher velocity. Note that the red hemi-row select lines are separate for each hemi array of sense amps (this will become important a little later). The overall die overhead compared to a standard SDRAM (DDR-SDRAM) chip is estimated to be in the order of 1.4-1.7 %. That means that the overall chip size will be roughly 1.4-1.7% larger than with a conventional design.

Shown above is a schematic of the EDDR architecture, which combines a standard DRAM array with an integrated row cache. The array itself with its interleaved bitlines is identical to the standard DRAM layout, however, here it is where the similarities end. The most obvious deviation from a standard design is the complete omission of column select lines.

The logical question in this regard is:

• If there are no column select lines, how can the correct data be selected?

• They don't have to, at least not on the level of the DRAM array.
• However, the SRAM row cache is direct mapped to the DRAM columns.
• Therefore, an entire row can be prefetched or precached into the SRAM cells using a point-to-point protocol.
• Consequently, any read command only pulls the data from the SRAM row cache.

There are quite a few advantages to this design. Consider this. In a standard SDRAM (or DDR), a row or page needs to be kept open (active) in order to allow for read commands to be issued. If a page miss occurs (about 70% probability), the row needs to be closed which involves moving the data back to the cells of origin and the entire array needs to be reset via a precharge. This process occupies 2-3 penalty cycles which add to the page miss latency. With EDDR, however, as soon as the data are latched into the SRAM cells, there is no need to keep any page open, all the memory controller needs to do is to issue an AutoPrecharge All command and the array is ready for the next bank activate command WITHOUT ANY FURTHER LATENCIES.

As a result, on a page miss without data still being in the CPU pipeline, the latency for the next critical word to be output is, on average, 1/3 less than in a standard DRAM part. On a statistical basis, the average (usable) bandwidth of EDDR in real life situations is approximately 27 % higher than that of standard SDRAM.

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