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Inside the EDDR Chip
Combining DRAM storage and SRAM speed
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(Review by MS, November 27, 2000)
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Power Issues
Speed, as much as we all like it, is not the only advantage of EDDR. Companies like Transmeta have made it their religion to save power wherever there is a chance. Power saving features are becoming standard at AMD and ALi as well since the mobile market becomes increasingly important.
A standard SDRAM DIMM in standby (suspend to RAM; STR) mode, consumes about 1 milli Ampere (mA) power because the clock input (CKE) can be turned off. The same DIMM, with the clock input active will increase its power consumption to roughly 50 mA. In case a page is kept open, the power consumption can further increase to some 90 mA. Please keep in mind that these numbers depend on the specifications of the individual chip manufacturers and can strongly vary even between different chips of the same manufacturer. The importance of this power consumption issue becomes obvious from just looking at the memory controller instructions issued by Transmeta, forcing a mandatory closing of any open page after 8 page hits. It is possible to do this, for the simple reason that most of the data needed are contained (prefetched) in the CPU cache, and on the rare occasion that require additional system memory accesses, the row can be opened again, with the side effect that it is already precharged and ready to go.
Savings of 99%?
How much power can be saved by precharging a row (closing the page)? It depends on how the contoller operates. That is, just closing a page and precharging the DRAM array so that it is in idle state can be used for will reduce the power consumption of the DRAM array from some 90 mA to about 50 mA, resulting in a roughly 45 % power reduction. This, however, is just the beginning since there is also the possibility to turn off the clock input to the array and put the entire DIMM into idle state. In this case, power requirements of the DIMM are at the level of STR, approximately 1 mA. This is no less than a 99% reduction in power and, more importantly, heat generation in the DIMMs. At the same time, data can still be read out of the cache. Wake up latency from a clock input shut-down, in case the SRAM cache needs to be refreshed can be held as low as 1 bus cycle which, in office applications will go unnoticed.
What are the drawbacks of EDDR?
Essentially, there aren't any, at least not on a performance level since the parts are 100% backwards compatible with standard DDR. The only issue is the die overhead of ca. 1.4% which corresponds to pricing overhead of less than the hourly fluctuations in the chip market.
next page: => Other possiblities and final words =>
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