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What else could be gained by EDDR?

There are a few issues but in order to explain them, it is necessary to go back to the design layout shown above. In the optimal scenario, each row activate command would automatically transfer all data contained in the row into the row register (cache). Consequently, all read commands could draw directly from the SRAM cells, which would dramatically speed up the CAS since there are no trace delays involved. In order to accomplish this, the command issued by the controller (chipset) would have to be altered but this is relatively easy to do. Particularly in a server environment where most accesses are totally random, cutting down the latency would dramatically enhance the performance, even if the bus frequency needed to be reduced.

Remember the need to use hemi-rows instead of a single full row? In order to cut the number of data lines in half, the proposed EDDR design calls for a time-multiplexed transfer between the (DRAM) memory cells and the SRAM cache. With a split arrangement of 2 hemi-rows, this is easy to do since, in consecutive clock edges, the data from the first set of primary sense amplifiers can be transferred followed by the second set of data. This way, each data line serves two sense amps, furthermore, the peak power consumption is spread in a temporal fashion. In theory, with high speed DDR parts, it is even possible to use quarter rows and distribute the array-to-SRAM transfers over four clock edges.

Summary diagram of the proposed layout with the time multiplexed buses (data lines) from the array to the SRAM cache

Conclusion

At the point where conventional DRAM design approaches its limitation, a hybrid memory design combining the advantages of both DRAM and SRAM in a single array offers substantial increase in average (usable) bandwidth by reducing latencies and simplifying the overall layout. Additional benefits include power saving features.

It is clear that at the pace at which microprocessor clock rates are developing, system performance will be determined by the bottleneck of the I/O system. Increasing amount of system memory have aided in moving this bottleneck away from the storage media, however, the lag in the memory performance, particularly with regard to latencies has created just another bottleneck. One can speculate that even with DDR-II and a 400 MHz data rate interface, the point of diminishing returns for CPU clock speed will be reached at or slightly above 2 GHz. Novel, low latency approaches of memory architecture will provide greater performance increase on a system level than the MHz race of CPUs. The most simplistic and economic approach to attain this goal appears a hybrid DRAM/SRAM architecture using a direct mapped cache as proposed in the form of EDDR. On a side note, if accepted at JEDEC, EDDR will lose its name and become standard DDR (II).

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