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SIMMs

Probably the smallest of the numerous upgradeable components in the personal computer are the memory modules (MM). Originally conceived as single chips, either soldered onto the mainboard or, in advanced designs, coming in the form of memory chips that could be stuck into already present sockets, they soon made the transition to a more advanced design, the single inline memory module (SIMM). With increasing demand for the storage and delivery of data impulses, the form of these SIMMs changed from the original 30 pin design to the more advanced 72 pin modules allowing a total of 32 bit bandwidth for the data path to the main bus. Still, the rate of data delivery lagged eons behind the capabilities of even the 486 processors which made a number of improvements necessary in order to feed the CPU with an adequate amount of information.

The most important step in this regard was the implementation of cache modules on the main board as well as on the CPU itself, both of which served as buffer for the "stream of consciousness" within the computer, as well as a retainer of the most recently called instructions and/or their addresses on the main memory (RAM). This by itself already caused an enormous increase in performance since the CPU did no longer have to scan the entire amount of system RAM for a given instruction, a process that anyway became more and more difficult with the steadily increasing size of system RAM.

Still, the overall bandwidth of the RAM to bus transfer in SIMMs was not increased over the 32 bit path and, thus, starting with the original Pentium CPUs, all further processors required the presence of SIMMs in pairs for an additive combination of the two 32 bit paths into an interlaced 64 bit data path. Last, like the original memory chips, even the latest EDO SIMMs are running in asynchronous mode, that is, at a fixed speed dictated by the SIMMs themselves rather than being tacted by the system bus.

BEDO RAM

Meanwhile, as CPUs further evolved, a number of measures were taken to further increase the data flow. Probably the best design was the addition of a burst mode to the asynchronous SIMM design which basically means that the first address of an instruction internally leads to the subsequent addresses without having to waste another clock cycle for the specification of a new column address. This so-called BEDO design would have combined the proverbial stability of asynchronous SIMMs with the speed of SDRAM up to at least 100 MHz. However, several memory manufacturers had already invested substantial amounts of time and money into a different design. In retrospect, it appears as if Intel's decision to not support the BEDO design and rather concentrate on SDRAM was only the first step towards total control of the market by optimizing the PC-100 specifications for their own (Intel) chipsets. Consequently, a superior product fell victim to politics and never saw the light of the day

The most important design change was to physically unite one twin pair of SIMMs to a so-called dual inline memory module (DIMM) blessed further with a 64 bit data output path and, thus satisfying the demands of the CPU in a single module.

Moreover, these new memory modules were running synchronous with the bus speed, that is, one bus cycle actually equals one memory cycle. This type of memory, the synchronous DRAM (SDRAM) is now found in basically all modern computers. In the beginning, SDRAM was often plagued with timing inaccuracies but the addition of a little EEPROM on the DIMMs has solved this problem in the form of serial presence detect (SPD). With this in mind, what could be more efficient for an increase of throughput than raising the bus speed? Well, I didn't invent this concept but it has been applied successfully over the last 5 years with system bus speed first being raised to 50 MHz, later to 66 MHz (with a few steps in between) and last not least the 100 MHz and more system bus speeds. If this sounds like old news now, just step back a few months and recall the excitement when Tom Pabst mentioned that he had a pre-series mainboard with a 100 MHz bus but it was so secret that he couldn't even hint at the source (that was before he got the Hong Kong flu).

And now, it looks like the system memory, once again, has become the slowest component in the chain of data flow and SDRAM will be obsolete soon, despite all efforts going into the PC-100 specifications.

Why is this happening? The answer is quite simple but before I can give it, I have to introduce the concept of RAM and I'll try to do it in form that everyone can understand (and I apologize to the experts if I dispel some of the myths).

Next question, where will we go from here? That's a tough one but I'll try to give some ideas about that.

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