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ESDRAM a New Memory Technology for Improved Utilization of Bandwidth
A preview
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(Review by MS)
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There are a few new technologies on the horizon that increase bus utilization. A case in point is Enhanced SDRAM (ESDRAM) that evolved from the original Enhanced DRAM (EDRAM) or Dynamicache used on Ocean 486 DCA2
motherboards.
What is the concept behind the name? For once, faster DRAM that could
actually run at a 6 ns clock cycle or 166 MHz bus frequency. Still, simply
increasing the burst rate without improving the underlying DRAM random
access speed would only lead to less bus utilization.
So, what else is so new about ESDRAM that they were actually granted the
approval as a new class of memory by the JEDEC committee? It is an extra
amount of cache added to the sense amplifiers called the row register cache
which, when the read command is issued, can instantly absorb the information
copies generated by the sense amps. Thus the sense amps are relieved
immediately of their ballast, even before data output begins.
Above, we saw that the limiting factor for the start of the next read cycle
was the necessary restoration of the empty memory cells to their original
condition by the autoprecharge. This process cannot be initiated before the
data are released by the sense amplifiers. If this event were accelerated to
occur simultaneously with the release of the first word, the autoprecharge
might as well happen immediately thereafter and be completed while the
second word is being transferred to the system bus (L2 cache). And that is
exactly the purpose of the row register cache. To spin this a little
further, at the release of the third word, a bank activate command can be
issued and the next read command can occur during the release of the fourth
word. Consequently on a page miss in the same bank, there is only one cycle
during which no output occurs. Random accesses to other banks don't even
have any delay. This type of RAM is, indeed, capable of delivering 4 words
in a row, interrupted by either one cycle or no cycles of non-transfer
before the next release starts. All in all, this translates into utilization
of greater 80% of the bandwidth available.
One picture tells more than 1000 words and one animation shows more than 1000 pictures which is why I am trying to show the flow of data in a side by side comparison of SDRAM and ESDRAM. Please be aware that these animations constitute rather large files and, thus, the loading may take a little while. Also, since some of the processes like internal data movements are not exactly synchronized with the clock cycle, there are some (very) minor deviations from the real life timings.
next page: => view animations =>
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