LOSTCIRCUITS

This animation simulates a real life data transfer situation where a continuous stream of information is requested from the DIMMs. The refresh rate of the animation is timed to equal 100 MHz (according to the PC-100 specifications). As you can see, only in 4 out of 9 clock cycles there is actual transfer of data (red balls) from the DIMMs to the system bus (in this case L2 cache), the remaining clock cycles are used for internal movement of the data and their duplication. Autorefresh cycles are not included in this demonstration.

Again, we are looking at a simulation of a real life situation in which a large amount of data has to be moved from the DIMMs to the system bus (L2 cache). Situations like this occur e.g. in graphics applications or importing/exporting clipboards. The refresh rate of this animation is timed to equal a 133 MHz bus clock frequency, compared to the 100 MHz in the SDRAM simulation on the left. In situations like this, the hidden autorefresh and the earlier bank activate command enabled by the implementation of the row register cache (RRC) bear full fruit since the available bandwidth can be utilized by 80%. That is, 4 cycles of data output are interrupted only by one cycle without data output.