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Aside from the system bus speed, what are the other factors that decide over the quality and quantity of the data throughput. In the preview of the Enhanced Memory Systems upcoming ESDRAM we have analyzed some of the factors and I quote:

The easiest way of looking at DRAM memory is to use the analog of a spreadsheet organized into rows and columns of individual cells. Each cell consists of a capacitor that carries a charge that represent a bit of data. Moreover, a row of cells is connected via the data bit lines to transistors that function as sense amplifiers. Words are selected from the sense amplifiers to the output pins of the DIMM. There is typically one sense amplifier per memory column.

1. The typical cycle starts with a bank activate command that selects and activates one bank and row of memory through the input pins.
2. During the next cycle, the data is selected onto the data (or bit) lines and moves towards the sense amplifiers.
3. When the data bits reach the sense amplifiers the data is latched by an internal timing signal.
4. This process takes length of time called the Row Access Strobe to Column Access Strobe delay (RAS to CAS delay) with a latency of usually two or three cycles.
5. After this delay, a read command can be issued along with the column address to select the address of the first word to be read from the sense amplifiers.
6. After the read command there is a CAS delay or latency while the data is select from the sense amplifiers and clocked to the output pin.
   The CAS latency is typically 2 or 3 cycles. Once the data is released to the bus, another word is output every cycle until the data burst is complete.
7. Only after all the information has been output, the data can be moved back from the sense amplifiers to the row of cells to restore its contents. Movement of the data back to the empty cells again takes 2 to 3 clock cycles.
8. Depending on the leaking or bleeding of the memory cells, the quality of the charge may have to be restored during a so-called refresh cycle. The need for a recharge is determined by a refresh controller whereas the actual process of refreshing is monitored by the refresh counter. This refreshing requires additional 7-10 clock cycles during which the data flow is interrupted and, thus results in a performance hit.

Now, one more time but with emphasis on timing issues:

1. bank activate (Clock Cycle 1)
2. data movement to sense amplifiers (Clock Cycles 1-2)
3. read command and CAS latency (Clock Cycles 3-4)
4. output of the first word (Clock Cycle 5)
5. release of one word per data cycle until end of the data burst (Clock Cycles 6-8)
6. Movement of the data back to the memory cells of origin (autoprecharge, Clock cycle 7-8)

Thus, all cycles involved in the release of one cache line fill of 4 words result in no less than 7 clock cycles (in the case of CAS Latency 2 DIMMs) before the next bank activate command can be issued. In the case of CAS Latency 3 DIMMs one has to add 3 cycles, one for the RAS to CAS delay, one for the CAS itself and one for the precharge to bring up the total number of cycles to 10.

So, what do these numbers tell us?

First of all, it is quite easy now to calculate the theoretical performance hit resulting from switching to less aggressive timing settings. That is, the time required for the transfer of a 4 word cache fill at 100 MHz will increase from 70 for CAS latency 2 (2:2:2) to 100 ns for CAS latency 3 (3:3:3) parts. This is not too bad, considering the prevailing price difference between CAS-2 and CAS-3 DIMMs.

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