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HSDRAM, Hi-Speed DIMMs beyond PC133
The latest from Enhanced Memory Systems
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(Review by bighammer, edited by MS, March 27, 1999)
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Some more technical considerations
From the above, it should be clear that the overall transfer highly depends on the so-called CAS factor. The important word here is "timing", that is there are 3 parameters that can be modified to increase or decrease the overall throughput being the RAS to CAS delay, the CAS itself and last no least the precharge. In other words, by reducing the number of cycles required for each of these processes, the utilization of the bus transfer can be sped up from 4 words / 10 clock cycles to 4 words / 7 clock cycles. This translates in an enhancement of the absolute transfer rate from 40% to 58%, resulting in a 45% higher data transfer. Needless to say that these aggressive timing settings require highly advanced hardware.
These are the candidates, on top is the 64MB DIMM, at the bottom the 128MB module, each equipped with 4.6ns (tAC) chips.
The hardware in this case involves the printed circuit board (PCB) with well laid out traces centered around the actual memory chips that, in the case of 133 MHz need to comply with a clock cycle time of 7.5 ns or less. There are already quite a few chips on the market that already claim 6 or 7 ns potential. However, 6 ns do not equal 6 ns because some vendors still generously mix the definitions of clock access time and clock cycle time. A clock cycle spans over a full cycle of alternating current that oscillates between 0 and V I/O (typically 3.3V) in a ramped "square wave" function where the thresholds of input voltage low and high (VIL and VIH) are usually set at 0.8 and 2.0 V. The mid-voltage between the two values is the crossover point (VTT) at 1.4V.
Memory chip used on HSDRAM, the chip part number is partially blurred
(sorry but these are preliminary chips and the numbers will change in the final version)
For the latest info please check the new PC-133 memory homepage
Clock access time (tAC) defines the time interval from VTT of the rising phase until output is generated, whereas the clock cycle time is defined by the frequency at which the system clock operates and has to be able to contain both the clock access time and the setup time as well as the time to phsically move the electric charges towards the output pins. More precisely, the two latter components require approximately 2.5 ns, leaving about 5 ns for the clock access time if the chips are supposed to work reliably at 133 MHz.
Since the clock cycle time has to contain the summation of 2 different components, the logical apporach would be to shorten both. However, the rise and falling times of the memory clock cycle largely depend on the interplay between the memory chips themselves and the system clock. What that means is that the system clock generates alternating current (AC) oscillating typically between 0V and 3.3V. In order to reach the holding plateau, the clock (CK0 or CK2) has to charge the DIMMs which requires a certain amount of time (the rising time). Similarly, in order to go back to 0.8V the reciprocal process needs to take place. Under perfect conditions, one would look at a square voltage function, however, as freqencies increase, the timing intervalls decrease and because there is no null-time charge or discharge, the steepness of the slope becomes a matter of temporal resolution. It is necessary to keep in mind that the voltages generated are a feature of the chipset rather than a feature of any memory module in the system, thus no matter of how a memory module is designed, the rising and falling times are constant factor of the chipset / board rather than the memory used. Thus memory manufacturers can make the best DIMMs but if the chipset clock does not hold up with the requirements for keeping the rising and falling times short, it is an uphill battle.
In other words, looking at the requirements for PC100 memory, the maximum allowance for the clock access time is 10 ns - 2.5 ns = 7.5 ns. Since the rising and falling times are unchanged with increasing bus speed, the tAC has to be shortened to 7.5 ns - 2.5 ns = 5 ns. If one goes one step further, e.g. 200 MHz, the clock cycle time will be 5 ns, leaving only 2.5 ns for tAC. Therefore, doubling the bus speed requires memory chips that are three times as fast.
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