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Taking the load off the DIMMs and future chipsets

There are a few other interesting aspects to this. If one postulates that each unit of memory has the same capacitance and resistance, the next logical step is that increased amounts of memory, because of their increased capacitance will actually slow down the charge / discharge times simply for the fact that the system clock will have to deal with a much greater load than if the memory amount was limited. Still, the synchronization of the bus clock requires that everything obeyes a master clock, at least at present.

Starting in the second half of 1999 several new chipsets will be introduced that try to overcome these problems by implementing individual clocks and registers for each DIMM slot. This way, the overall load for each clock will be reduced, resulting in faster rise and fall times of the voltage and thus leaving more headroom for tAC. This, however, will open another bag of fleas because all clocks will have to be precisely in tune, which can be done by a phase lock loop in which the individual clocks are triggered to the exact same starting point. The trigger itself will require an additional penalty cycle, however, the higher possible bus speeds will more than compensate for the performance hit. One step further, because not all DIMMs are equal, will be a possibility to fine-tune each clock according to the load it has to deal with and to compensate for the skewing of the individual wave forms caused by the different characteristics and capacitance of the memory driven. All of this is quite reminiscent of a battery of double barrel carburettors where each barrel needs to be adjusted individually. However, using this kind of technology, the projected DIMM speed will be approaching 200 MHz or higher.

PC 133

Spearheaded by Micron Technology, there are new DIMM specifications that are currently under review at JEDEC (the organization that sets the standards in memory technology). According to Micron's specifications, the new PC-133 DIMMs will employ 5.6 ns chips. In view of the above, there is very little if any headroom in this case for reliable performance at 133 MHz, accordingly, some of the other parameters have to be increased to assure that the system clock will not overrun the DIMMs. The easiest way to achieve this, of course is to add penalty cycles, that is, setting the strobes for row and column access (RAS and CAS) to a latency of 3 cycles each, in addition to add one more waiting cycle for the precharge. This way we are looking at a timing setting of 3:3:3 that can be achieved at 133 MHz without too many technical difficulties. In fact, there are some PC 100 DIMMs out there that are good enough already to fall within the new category.

Beyond PC133

Colorado Springs has, as of lately, developed into a chapterhouse of hi-tech memory R&D. One of the local companies, Enhanced Memory Systems, has recently introduced the concept of adding row register cache to the DIMMs themselves, thus achieving unprecedented utilization of the memory transfer bandwidth of over 80%. The new DIMMs are specified as ESDRAM, and the importance of additional cache levels within the memory-to-CPU path is eminent from the performance boost that the AMD K6-III receives from its TriLevel cache architecture. Unfortunately, no current chipset supports ESDRAM yet, however the tchnological know how is there and in order to bridge the time until the first ESDRAM supporting chipsets will be released by VIA and Acer Labs in Q3 this year, the logical consequence is to produce standard DIMMs that are just better than what the competition has to offer. This way there are no compatibility problems that the consumer has to be afraid of and it is also a good way to even the path for the next product. Above we mentioned the PC 133 specifications, however, compliance with those appears to be child play considering the technical know how and the quality of the chips used for the "Enhanced Memory Systems" DIMMs. There is of course the problem with the nomenclature since Enhanced SDRAM or ESDRAM follows a different layout, on the other hand, simpy adopting the PC133 name would sell short a superior product. In situations like this, often the only way out is to offset oneself from the field by creating a new name and since the Enhanced Memory System DIMMs are supposed to run at high speed, the nearest approximation for describing their features is High Speed SDRAM or HSDRAM.

Enough said here, a look at the spec sheet tells enough. The chips themselves are rated at 4.6 ns clock access time leaving ample 2.9 sec for setup time and electron movement down the data traces. One thing one needs to keep in mind here is that the clock access time is usually given with a certain amount of overhead, individual chips may vary in terms of their performance but all of them have to fall within the margins set by the specifications.

The test

Testing memory running at 133 and above FSB is not exactly an easy task. There are certain requirements that have to be met in order to do such high end modules justice. The first requirement, of course, concerns the mainboard itself, there is no use to go with a board that lacks stability at higher bus speeds or has known memory problems (like the Abit BH6), similar demands are to be postulated for the peripherals. By a landslide, the most stable and reliable mainboard currently avaliable is the ASUS P2B (F revision) that, in addition, offers settings for front side bus frequencies of 133, 140 and 150 MHz as well as the BIOS options to set the CAS latency to 2 (2:2:2) or 3 (3:3:3). Regarding the choice of the system peripherals, we ended up with the ASUS V3400 TNT graphics adapter, Creative Labs Voodoo2 12 MB 3D accelerator, Ensonic PCI sound card, Acer PCI modem, 3Com 10baseT ethernet card, WDC 6.4G HDD, Aopen 32x CDROM. All tests were run using the 1/3 PCI divider and the resulting frequency of 46 MHz was tolerated by all devices.

The main handicap for testing, however, turned out to be the CPU itself. With Intel's policy of multiplier locking, there is very little that can be done in terms of overclocking to FSB frequencies in the range of 133 MHz and beyond. Still, the older PII processors (before week 37 1998) are not multiplier locked and despite the fact that they are limited in their absolute clock frequency, there is a good chance to run a PII 333 at up to 420 MHz, that is 140 MHz x 3.

The choice of these peripherals took a bit of work but, to make a long story short, it was rewarded by very nice results. It is of utmost importance to stress this point since any component in the system unable to run under the test conditions would have falsified the outcome of what was intended to be a memory test and it did take a bit of experimentation to get to the point of cool running at 140MHz and CAS-2 settings. Needless to say that in a hushed or careless review we could have gotten stuck at 133 CAS-3 settings and blame it on the memory when, in fact, our own incompetence / poor choice of hardware would have been the culprit.

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