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The Test System

We have configured the following test system to measure the performance impact of different bus speed and latencies in synthetic benchmarks and real world applications:

• ASUS CUSL2 (Intel i815) chipset
• Intel PIII Coppermine FC-PGA (933 MHz, unlocked engineering sample)
• 128 MByte HSDRAM
• MSI MS-8809 Phantom GeForce 256 (SDR)
• IBM DPTA 372050 Deskstar.
• Hitachi 8x DVDROM
• Windows98 (second edition)

Why are latencies important? In short, latency means the time from when an access is issued until the critical data are available. Latencies are a universal phenomenon and a main determining performance factor for the CPU cache, the HDD (access time), the PCI bus and any other component of any computer system, including the main memory. This article focuses only on the latter factor, that is the system memory. For a detailed introduction of how memory works, the PC-guide has the most comprehensive information. A more compressed version of the different timing issues relating to performance is found in our own articles on ESDRAM, HSDRAM and Corsair PC 133 DIMMs. For those interested in more architectural questions, a good write-up has been posted on Aces Hardware.

Briefly, the current chipsets allow to vary three timing parameters:

• CAS Delay (CAS): 2-3 cycles
• RAS-to-CAS Delay (tRCD): 2-3 cycles
• RAS Precharge (tRP): 2-3 cycles

From these numbers, it is possible to calculate that, at 3:3:3 settings, a total of 10 bus cycles is necessary to release four words (Bytes). At 2:2:2 settings. the same would be accomplished within 8 cycles (precharge latency is not as important since the precharge can already start while the third word is output). Increasing either CAS Delay or tRCD to 3 cycles will result in 9 bus cycles / 4 bytes, however, this simple equation only holds for totally random accesses. In real life applications, CAS delay is much more important than RAS-to-CAS delay as we'll see in the next paragraph.

A simplified, three paragraph explanation of memory latencies

Data are written to and read from memory in a relatively ordered manner, that is, most of the time coherent data are stored within the same row (high locality) where only the column address changes, meaning activation of the Column Address Strobe only. From a performance standpoint, therefore, the most important of the three timing parameters is the CAS delay. Since this is important, I'll rephrase it one more time: most of the time, data that belong together are stored in contiguous blocks within the same row. In turn, this means that for consecutive single word or burst reads, only the new column address needs to be specified which which is then accessed by the column address strobe (CAS). If the data are not found within the same row, they have to be retrieved elsewhere and that involves delays from the bank activate command to the read command (RAS-to-CAS delay) and the CAS delay.

What about the precharge? Data are electrical charges that are coming out of the memory cell (1 capacitor) and after a copy of these data has been generated in the sense amplifiers, the original has to be moved back to the cell of origin and stored (precharge). The tRP latency is of minor importance since the precharge can start as soon as the 3rd word of a burst write is being output and, thus the latency is masked.

The specs of the various chipsets , e.g., the page hit limitation (PH limit) in the AMD 751 North Bridge allow to predict how many times data can be retrieved from within the same row, and even though the individual application plays an important role, we can estimate that a mandatory tRCD occurs only every 32to 64 reads (depending on the BIOS settings). Under normal circumstances, the counter treats any transaction alike, that is, it does not differentiate between single word and burst reads. Therefore, the CAS delay occurs as much 64 times as often as the RAS-to-CAS delay (This only holds for optimal conditions, in real life, the ratio would most likely be in the order of 10:1 or 20:1). More details details would fill a book but who would read it anyway?

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