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133 MHz change a few things

Since we have established the importance of latencies at low memory bus speeds, it is interesting to see what increasing the bandwidth by raising the memory bus speed to 133 MHz does for the benchmarks. The two important questions are:

• Many PC 100 CAS-2 DIMMs will run at 133 MHz, albeit, only at 3:3:3 settings. Is there really a performance gain achieved by this?
• Theoretically, one would predict that if bandwidth is less of a limiting factor, latency issues become more dominant. Thus, what is gained by running 133 MHz and low latencies?

SiSoft Sandra scores at 1 GHz to compare the memory bandwidth in MByte/sec at 100 MHz memory bus (2:2:2) , 133 MHz (3:3:3), 133 MHz (2:3:2) and 133 MHz (2:2:2). (2:3:2) CAS-2, tRCD-3, tRP-2

SiSoft Sandra shows that increasing the memory bus frequency at the expense of latencies only marginally increases the overall bandwidth. In other words, stepping up from 100 MHz and 2:2:2 latencies to 133 MHz and 3:3:3 only yields about 4.6% bandwidth increase, whereas reducing the latencies, once again is rewarded with a 23.4 % increase in bandwidth.

Claims have been made that at PC100 memory standards the mismatch between the external CPU frequency (often referred to as front side bus) and the actual CPU clock speed causes the CPU to choke on the unavailability of data. By extension, the same holds if the memory bus runs at a harmonic frequency, in this case, ¾ of the FSB. Consequently, at 133 MHz memory bus, lower latencies should cause a larger increase in frame rates than at 100 MHz since the bottleneck shifts from bandwidth to latencies. In other words, latencies become an overwhelming factor not only in the data transfer but, more importantly, in the performance equation. Expendable is, once again, an example:

Similar as in SiSoft Sandra, Expendable frame rates show only a 4% increase by stepping up from PC-100 (2:2:2) to PC-133 (3:3:3). Interestingly, however, reducing the latencies to 2:2:2 yields a 10% system performance increase as measured in frame rates. Leaving tRCD at 3 only causes a minor performance hit

With increased (memory) bus speed, the mismatch between the clock speed and the memory bus is less pronounced and, therefore, as shown here, bandwidth alone does not provide much performance edge if the frequency increase is penalized by longer latencies. Over the past few months Rambus has given a rather drastic example for the validity of this rule.

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