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Some Basics

There are a few other issues about die shrinks. Typically, the slowest part in the memory signaling chain is the summation of processes referred to as RAS-to-CAS Delay. RAS-to-CAS Delay or tRCD is the time after a bank activate command is issued until a read command can be given. In layman's terms, a page has to be opened before one can start reading its contents. In technical terms this is done by sending a signal along a wordline which then opens the transistor gates of all memory cells within this row or page. The memory cells then release their charges onto the bitlines where they are sensed and amplified by the primary sense amplifiers.

Programmable CAS latency requires mode registers and the necessary pipeline stages / bypass switches in order to work. More information below and in our BIOS Guide

The critical issue here appears to be a propagation delay of the opening of a page. That is, the wordlines that have been shrunk like everything else are becoming too thin and carry too much resistivity with them which then slows down the opening of the pass-gate transistors and subsequent sensing of the data onto the primary sense amplifiers. Note that all bits of the page that is being opened have to be sensed by the primary sense amplifiers before a read command can be given by the controller. Otherwise the read would be like looking at a printout done with a bad cartridge where only fragments of the text are legible.

If the line that carries the signal to open up the pass-gates is too slow, because of reduced width, the most common requirement will be to add an additional wait state or cycle to the tRCD, in other words, often the tRCD of die shrinks needs to be prolonged in order for the memory to function properly. Those who are interested in the gory details can find them in our earlier memory reviews.

CAS Latency

Unlike other latencies like tRCD or tRP that are flexible time intervals that can be changed on the memory controller level at will, the CAS Delay or Read Delay requires a hardware-based, programmable configuration of the DRAM output path. The original patent for programmable CAS latency goes back to RAMBUS. Briefly, what it means is that for every latency cycle (or hemi-cycle), a physical pipeline stage has to be inserted into the output path to temporarily hold data. Therefore, any memory chip can only run at the CAS latencies it was designed for. Programmable CAS latency means that there are bypass switches in the output path that can be used to bypass some of the pipeline stages, thereby lowering the CAS latency (see above).

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