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RAS Pulse Width (tRAS)

Over and again, we stumble across statements highlighting a short tRAS as a performance feature. This may be true for pseudo SRAMs or 1T SRAMs operating at a burst length of 1 and totally random accesses in non-paged mode. In that case, the time necessary to build up the voltage differential between a bitline pair that is required in order to restore data after a destructive read, also called the RAS Pulse Width, is the limiting performance factor.

However, in standard PC SDRAM, a short tRAS completely misses the point, regardless of whether it is single or double data rate memory. The reason is very simple. tRAS defines the minimum bank open time, that is, the time after a bank activate command until the bank can be closed again. An analogy would be the time that a reader is allowed to look at the page within a book. By definition, no page can be closed before it has been opened, and it does not matter whether it is a book or a piece of memory.

Therefore, tRAS has to be at minimum the number of tRCD plus CAS latency cycles. This rule applies for single data SDRAM. Keep in mind, though, that DDR is only capable of playing out its strength when a burst length of 8 quadwords (that is, 8 transfers per pin) is used. tRAS is the minimum page open time, therefore, the minimum requirement has to be that tRAS equals tRCD plus CAS DL plus a minimum of 2 cycles to output the first four quadwords and move the second half, that is the remaining four bits into the output buffers to pipeline the second half of the "Burst of 8".

The original drawing of the heatspreader used by OCZ, Kingston and a number of other vendors goes back to December 15, 2000. Note the author of the design.

Once those data are in the pipelined output buffers, the bank can be closed. If, however, the number of cycles specified above is undercut, it will result in truncation of data bursts, which is synonymous with performance degradation and potential data corruption. The best documented examples are numerous cases of HDD corruption, especially in RAID 0 configurations, however, there is also performance degradation if tRAS is set too short.

Bottom line for DDR technology is that, as a rule of thumb, for best performance and stability, tRAS should never be less than the sum of tRCD + CAS Latency + 2 (or more) cycles.

Precharge

Before a new row can be opened, the data have to be restored to the memory cells by writing them back and closing the gate transistors during the precharge cycles. The number of precharge cycles depends on the frequency as well as the performance characteristics of the chips used and can be set in the BIOS without having to program any specific registers on the DRAM.

Low Density vs. High Density

We mentioned already that the die size is inversely correlated to the potential speed at which the memory can run and that this is one of the incentives to migrate to smaller interconnect technology. Another possibility to keep the die size low is to use lower density, a typical 256 Mbit chip has twice as many rows as a 128 Mbit chip, the column addresses / row, however remain the same. Overall, the die is still smaller which means that it will be faster to get the data out of the array.

With this preamble out of the way, it is time to take a look at a rather interesting piece of memory: OCZ PC3700 EL DDR Gold Dual Channel. How much is gold here and how much is glitter.

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