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Summary

AMD Opteron and Athlon64 FX dual memory channel CPUs require registered ECC DDR400 DIMMs. According to the latest JEDEC specs, those modules are supposed to be built using BGA components instead of the standard TSOP form factor, and consequently, as we were informed by AMD, modules built with the older TSOP components will not be qualified. Currently, the only DIMMs that are qualified are those sold by Kingston under the HyperX brand name, which, unfortunately are blessed with very high latencies, that is 3 cycles for each CAS delay, RAS-To-CAS Delay and Precharge delay.

Other vendors are disregarding the lack of "qualification status" and offering low latency DDR modules based on conventional TSOP designs. In terms of functionality and reliability, there does not appear to be any advantage of the BGA design, on the contrary, the very rigid solder connections on a flexible PCB actually make for a much more fragile design than the mechanically more forgiving TSOP form factor. And what about performance? We have analyzed a handful of the new modules under various conditions and the results are surprising to say the least.

It was only a week ago but already it appears like the distant past, that AMD officially released the Athlon64 and its up-scale version, the Athlon64 FX-51. In all the euphoria about the new processor were some skeptic voices, criticizing the necessity of using Registered DDR DIMMs because of cost issues and also, because Registered DIMMs add additional latency cycles to the initial access. To add to the confusion, these Registered DIMMs are also capable of running error checking and correction (ECC) which, admittedly adds additional performance penalties.

Today's candidates: Clockwise: Kingston HyperX Registered ECC DDR400 (3:3:3), Legacy Registered ECC DDR400 (2.5:3:3), Samsung Registered ECC DDR400 (3:3:3), Mushkin Registered ECC DDR400 (2:3:2) (click for larger image).

Some Clarifications

Briefly, ECC has nothing to do with Registered DIMMs, it is mere coincidence that the two features are usually implemented together for the simple reason that the boards that require Registered DIMMs are usually working non-stop and have a need for ECC to avoid accumulation and propagation of soft errors that occur statistically over time. For the memory vendors, the trade-off of carrying Registered non-ECC modules is a double inventory and, therefore, the savings incurred by leaving off one chip per bank are not worth carrying two separate lines of memory, especially, if the non-ECC modules are only geared towards a splinter cell of user.

Keep in mind that having ECC capabilities does not mean that the ECC features need to be turned on, on the contrary, the different ECC modes can be completely disabled if the emphasis is on performance rather than on prevention of error propagation.

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