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On to RAM Stress Test

The above mentioned benchmark utilities are niceties, however, the core of RST-Pro is the actual RAM Stress Test which is running a series of standard and proprietary patterns throughout the entire memory array. A detailed explanation of the different routines would exceed the scope of this article, suffice it to say that patterns include walking through every single bit in the array in ascending and descending order, random jumps, copying blocks of data as well as checkerboard patterns. Briefly, a checkerboard pattern is to write alternating 0 and 1 throughout the entire array to establish whether accidentally some bits are coupled through cross-talk or other unwanted interferences. Other tests include reversing the addresses, which is extremely painful for the row and column decoders. Aside from running the "standard" that is the most common tests, RST-Pro offers to customize the selection of tests. In addition, as mentioned earlier, the PCI register editor allows to change BIOS settings even if they are not supported by the layout of the particular mainboard BIOS interface in similar fashion as WPCREDIT. This allows to change memory timing parameters on the fly. The only drawback is that it is necessary to know the binaries of the particular chipset since there are not explanations regarding the different offsets and the byte code.

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At the end of any analysis, RST Pro generates a report about the errors encountered and their location. From a practical standpoint, the standard display is actually more revealing since the location of the errors within the 64 bit width of the bus pinpoints the exact chip that fails.

With any standard x 8 (8bit wide chips) module configuration it is easy to find a failing chip. Just keep in mind that each chip is 8 bit wide

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There are special cases where things are a bit more complicated. One example are DIMMs that use 16 bit wide chips which means that the chips are divided into a so-called upper and a lower block of 8 bits width each. The naïve assumption would be that the upper and lower blocks of any chip form a coherent 16 bit wide stretch, in reality, this is not true since the lower blocks of each chip are found within bits 0-31 while the upper blocks of the same chips map to bits 32-63. This can be rather confusing since a single bad chip will show up in two separate areas of the bus width. <

Overclocking and Reliability

Shortly after RST Pro became available, Joe Citarella from Overclockers.com and I started arguing whether an overclocked PCI bus would affect the reliability of the device in detecting errors or else generate false positives, that is report errors where none occur. Joe claimed it wouldn't, I claimed it would and Joe was right because RST-Pro does not appear to have any problems at even excessively high bus speeds.

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