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August 7, 2000
Summary
ASUS has, once again, created a masterpiece of a mainboard with superb stability and about any option one could ask for, except for the lack of an ISA slot. Because of the possible jumperless configuration, the A7V provides an excellent platform even for the inexperienced user. The Award Medallion BIOS allows fine-tuning of performance features from within the Advanced / CHIP Configuration which can be used to adjust the chipset parameters to the rest of the system hardware configuration. By using these options, the more sophisticated user can push the system performance to dwarf the competition.
A Quick Intro to Thunderbird
One of the potential downfalls of the original Athlon has been the backside L2 cache. While the overall size of this L2 warranted a substantial capacity for caching data and addresses, its overall contribution to the system performance was hampered by its distance from the core and the relatively low frequency of the cache SRAMs used. The typical range of these SRAM chips was in the order of 300-375 MHz running at ½ clock speed in the first series of Athlon. Since SRAMs have a speed limit, the only way to crank up the clock speed to as much as 800 MHz without exceeding physical and economic limitations was to use a programmable cache divider keeping the operating frequency below 400 MHz. In other words, a ½ cache divider is viable only up to about 750 MHz, whereas the next step down, a 2/5 divider could possibly go up to 900 MHz. Above that, the cache divider needs to be set to 1/3 of the clock speed.
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Since data transfer between the L2 cache and the CPU is one of the most crucial parameters in overall system performance, it is clear that the growing mismatch between clock speed and cache speed may cause some non-linearity in the performance gain relative to the increase in clockspeed. The solution to this problem, as demonstrated by Intel’s Coppermine CPU is to move the L2 cache on-die and run it at clock speed. Actually, the concept had been introduced earlier with the Celeron and further with the AMD K6-III, both cases delivering blazing performance at the time.
AMD Athlon Thunderbird (courtesy of AMD)
Integrating a high-speed cache on-die, however has a few other problems. As a rule of thumb, cache size and speed are usually inversely correlated. In other words, the faster the desired cache SRAM is supposed to be, the smaller needs to be the actual size of the cache. In order to satisfy the demands on L2 cache for a high end CPU like the Athlon Thunderbird, the L2 cache needs to maintain a minimum size of at least 256 KByte which appears to be about the upper limit of what is currently possible to run at 1 GHz.
Contrary to DRAM where each bit storage capacity needs one capacitor, SRAM is composed of transistors and the most current technologies are based on either four or six transistors per bit. Using the latter design, this increases the overall transistor count of the CPU die by
6 (transistors) * 1024 (kilo) * 256 (bytes)* 8 (bits per byte) or roughly 12.6 million transistors
Add a few peripheral transistors and you add up with about 15 million transistors, which is roughly the difference between the old (22 million) and the new Athlon (37 million) core.
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