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Memory Subsystem / SiSoft Sandra 2002

As already mentioned, running the memory bus at 166MHz or at 5:4 harmonics of the external CPU bus requires some mechanisms to translate the higher memory speed to the same data rate at which the EV6 bus is running. These mechanisms include serially connected buffers that accept the data on one end and spit them out at the other side. Suffice it to say that each buffer stage requires an extra clock cycle until the data are forwarded, in other words, the extra latencies eat up a substantial amount of bandwidth. Exacerbating is that, since the CPU bus runs at 266 Mbsp (Megabit/ sec and pin) and 64 bit width, there is an a priori limitation to 2100 MB/s between CPU and chipset that cannot be exceeded.

Buffering Enabled essentially means that prefetching is allowed and the memory bus is operating under optimized, streaming conditions that are limited mostly by the page size and Page Hit limitations (if those are imposed by the controller). With an optimized path, current high-end systems are capable of achieving up to roughly 95% bus utilization. That is, with a PC2100 interface, bandwidth rates of 2050 are not uncommon. The big question is, how the asynchronous memory bus behaves under these conditions, especially since, as mentioned above, the CPU bus cannot handle more than 2100 MB/sec in the first place.

SiSoft Sandra Memory Benchmark results depending on BIOS settings and memory frequency. All results were obtained using the "Optimized" setting unless indicated by "Turbo", all runs were done at 2:2:2, 1T CMD Rate and 6T tRAS except for those at 4:5 (CPU : Memory Frequency) and SPD where the latencies were increased to 2.5:3:3, 1T CMD Rate and 6T tRAS. At the Optimal setting and 133 MHz memory bus, the bandwidth is slightly lower than at the 166 and SPD setting. Lowering the latencies at the 166 MHz setting does not buy very much, consistent with the idea that the bottleneck is in the chipset rather than in the actual memory. Moving to the "Turbo" setting, increases the PC2100 performance beyond the highest scores we got out of PC2700 operation. Increasing the bus frequency shows pretty much the same picture.

Buffering Disabled

WIthout buffering, prefetching is disabled which means that there is no real data streaming possible, even though accesses can stay in page. This naturally reduces the overall bandwidth and consequently, the chipset and bus bottlenecks are no longer as limiting as they were in the streaming application. Therefore, it is not too surprising that bandwidth gets the better of latencies, meaning that the higher memory frequency shows slightly better results.

SiSoft Sandra Memory Benchmark results with buffering disabled. Note that higher memory frequency gives better results than lower latencies, however, the difference is only marginal. Needless to point out that increasing the CPU bus frequency yields better gains than increasing the memory frequency.

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