L O S T C I R C U I T S

July 10, 2000

There is no doubt that Intel is making excellent CPUs. Some doubts, however, have surfaced lately about the validity of Intel’s claims to fame with their chipsets. After all the hypes that the BX chipset is finally at the edge of obsolescence because of the lack of AGP x 4 support as well as the inability to offer the ½ AGP bus divider and some other smaller issues, Intel has gone through reiteration after reiteration of their i8x0 chipsets, only to leave a stale taste behind.

To be true, none of the solutions offered by Intel were really bad. The i810 chipset, particularly in the i810E revision offered a low-cost integrated solution for a secondary PC at an excellent price performance ratio, and the i820 (Camino) isn’t too shabby either. Either chipset, if released one year earlier, would have blasted the competition, alas, the same argument was made for the AMD K6. Once again, this tells us that in today’s market time is virtually the most important issue and Intel is no exception. Regarding the i810 chipset, the main problems were the inadequate graphics capabilities and the lack of support for PC133 memory. The i820E was handicapped by the need for the overpriced Rambus memory which, at the same time, did not meet the expectations in its performance.

There comes a point, however, where the losses in major business become greater than the quick buck made on the stock market and, finally, we see a turnaround in the Intel politics. That is, suddenly, the frowned-upon PC133 SDRAM becomes a legitimate option even with the advanced hub architecture. The way to save face is quite simple, do the Münchhausen trick of pulling yourself by your hair out of the swamp by defining your own PC133 standards and get on with your life, which is why we have two different standards even though the Intel standards are remarkably similar to those spearheaded by Micron. Actually, this would be oversimplified, Intel rarely does anything without a specific reason.

In short, there are different latency parameters that influence the performance of SDRAM. The most crucial timing issue is the CAS latency or delay, whereas the precharge and RAS-to-CAS delay have only minor impact on the data transfer rate. Even with the most advanced memory chips, it is still difficult to fit 2:2:2 timing parameters into the 7.5 ns clock cycle time of the memory bus when running at 133 MHz. However, the latencies for the CAS delay, RAS-to-CAS and precharge can be internally shifted around and instead of defining a 3:2:2 (CAS-3) DIMM with lower performance, moving the 3 penalty cycles to the RAS-to-CAS delay offers about the same safety margin but with CAS-2 performance characteristics.

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