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May 2nd 2001
Summary
USING a DDR interface together with a PentiumIII is considered mostly eye candy since the CPU-to-chipset interface (front side bus) is running at single data rate. Therefore, regardless of how much bandwidth the memory bus provides, it is hardly conceivable that the additional throughput could be utilized by the CPU. Initial reviews confirmed this point of view.
Asus is in the process of releasing a second generation VIA Apollo Pro266 board, the CUV266. The review unit did not feature any integrated peripherals like sound or network and was as trim and lean as any possible performance mainboard can be. A few glitches still present in the preproduction version do not impinge on the overall impression that the CUV266 could easily outperform any i815 chipset based board in terms of both performance and overclocking capabilities. We were able to run the CUV266 stable up to 166 MHz with DDR data rates of up to 333 MHz and at these settings, the board takes any PIII to new performance.
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VIA's Apollo Pro266 chipset has been available for some time but there has always been the question of whether there is really any interest in outfitting the Pentium 3 interface (SDR P6-bus) with a DDR memory bus. The usual perception is that the memory transfer bottleneck might simply be moved from the actual memory bus to the front side bus or data path between the chipset and the CPU. The other side of the coin, of course, is that, wherever there is a bottleneck, changing the weakest link will be the most effective measure to increase overall performance.
Aside from a simple change in the memory interface, the new VIA chipset incorporates another important feature: VLink. Because not everyone is familiar with the VLink architecture, here is a brief description: Instead of using the classic North and South bridge architecture, connected via the PCI bus, the two main components are now termed Host and Client and are interconnected by a 266 MB/sec high speed interface. The new chipset components are evolutionary developments from previous VIA chipsets and thus carry over certain characteristics. At one glance, the important differences are underlined in the table below.
comparison between the new Apollo Pro266 and Pro133A chipsets
The main differences are underlined.
There are some more subtle differences between the older VIA chipsets and the Apollo Pro266. In none of the older diagrams of VIA chipsets are the clock signals included. The reason is very simple. The old chipsets only relied on the system clock, and in turn, the timing parameters of all devices were extremely vulnerable to unequal trace lengths. DDR by itself requires much tighter timing control than SDRAM and, therefore, a clock forwarding reference signal has been added. Take a look at the new diagram and keep the clock traces in mind for the rest of the review.
Summary diagram of the VLink archtecture and the interconnecting clock forwarding traces
Every trace with a CLK within the diagram is serves clock forwarding which will become more important towards the end of this review.
The first time encounter with the ASUS CUV266 dates back to January, at that time, some issues with the AGP data transfer were still unresolved that, on most VIA Apollo Pro systems, would cause the system to suddenly stall or else run at abysmally low performance. These issues threading through all Apollo Pro266 boards were resolved since but caused some delay in the market, before we could see mainstream release of VIA Apollo Pro266-based board. Let's check it out:
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