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May 2nd 2001
BIOS
The CUV266 uses the ASUS-standard Award Medallion BIOS with all bells and whistles. Typical for the VIA chipset, the CUV266 allows to run the memory bus in a harmonic frequency of the FSB, that is, either in 133:100:33 (CPU:DRAM:PCI frequency), 133:133:33 or auto mode.
Memory timing parameters can all be set individually, that is CAS latency (CL), RAS-to-CAS Delay (tRCD), Precharge (tRP) and RAS Pulse Width (tRAS). In addition, the Chip Configuration page offers the possibility to select bank interleaving mode (disabled, 2bank, 4 bank and auto). For a detailed description of the performance and stability issues associated with each of the timing parameters, please consult the LostCircuits BIOS Guide.
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Other features include setting of V core, AGP transfer mode, UC or USWC mode (uncached vs. uncached speculative write combine), as well as the usual suspects as PCI delay transaction (no longer a valid entry) and PCI latency timer (default =32 cycles, for better performance set to 64 cycles).
A typical Award Medallion feature is that, upon boot failure, it does reset itself to default settings, in most cases, the FSB is automatically adjusted to the CPU's frequency ID (FID). A similar feature is found in the CUV266, however, in this case, the system did not default back to the 100 MHz of the CPU FID but started repeated boot attempts until it settled at e.g. 150 MHz. This is interesting since it suggests that the system renegotiates a safe setting according to the user defined setting by defaulting to the highest workable frequency.
In theory, this is quite a step up from the safe setting approach used in the past. In practice, this routine can be rather time consuming since, in some cases, the system went through loop after loop before finding the appropriate setting. Another observation was that, after overstepping the FSB limitation of the memory at the shortest latencies, the system would boot up normally, that is, without stopping at the BIOS setup, however, the FSB was internally changed to e.g 150 MHz while, in effect, 155 MHz FSB was selected in the BIOS.
In other words, selecting the FSB in the BIOS does not always yield the desired frequency, it is necessary to either monitor the POST or else run CPUID to verify that the settings specified are, in fact, what is running.
Related to these glitches, the CUV266 refused to recognize any unlocked PIII engineering sample supplied by Intel. To be sure, this configuration is not what anyone outside the hardware reviewer group would possibly use but since the boot failure falls into vaguely the same category as the extended initialization before POST, it won't hurt to mention it here.
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