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| AMD Athlon64 3200+ - ASUS K8V Deluxe The Middle Grounds | |
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(Review by MS, November 3, 2003) |
| K8V Deluxe At: |
Summary
The Athlon64 has finally hit the stores, so have a few mainboards based on either the VIA K8T800 chipset or else on the nVidia nForce2 core logic. After looking at the Athlon64 FX-51 with its dual memory controllers and a price point that almost matches its 940 pins, we are taking a long look at the home edition of AMD's 64-bit processor, conveniently dubbed Athlon64 and a price point at slightly over ½ of its 754 pins.
Needless to say that a single channel memory controller does not reach the luxurious bandwidth of its dual channel counterpart, however, it may have some more agility, courtesy of supporting low latency unbuffered memory.
And then, there was the VIA K8T800 chipset, an interesting combination of a high performance AGP Tunnel and a South Bridge that is somewhat, er, difficult to categorize. Add a WiFi slot and the corresponding card, some decent AnalogDevices sound without the high-end Sensaura software and the result is the ASUS K8V Deluxe. Does it have what it takes to play in the upper division? You are about to find out.
The original Athlon64 platform was planned as something as simple as a 64-bit platform utilizing a memory controller with extremely low memory latencies. The one part of the core logic that is the most crucial for performance, i.e., the memory controller is already integral to the processor itself, therefore, the rest of the chipset appears to be a no-brainer, at least compared to the standard core logic designs.
That is, in case the memory controller is part of the chipset, it has to be smart enough to make intelligent decisions regarding the arbitration of DMA vs. CPU accesses. Likewise, most modern memory controllers are capable of doing one or the other form of prefetch, not only on the basis of locality, but also according to some data access patterns that are analyzed and then used for branch prediction.
If most of these features are relegated to the CPU and its integrated memory controller, then there is relatively little left for the IC formerly known as North Bridge, other than serving as interface between the CPU and the I/O controller as well as arbitrating the AGP traffic. It is not for nothing that the piece of silicon responsible for interfacing the HyperTransport interconnect with a link to any old-fashioned South Bridge is now called a tunnel, more specifically, the AGP tunnel.
VIA K8T800 chipset block diagram.
As shown in the diagram, the CPU connects to the K8T800 chip via a 16 bit full duplex HyperTransport link running at 1.6 GHz. This means that there are two separate 16 bit HyperTransport channels, one for the uplink, the second one for the downlink, each of which has a maximum bandwidth of 3.2 GB/sec for CAD (combined Command, Address and Data) packets. This duplex 16 bit interconnect between CPU and the rest of the system is where the VIA chipset has an edge over its nVidia counterpart. That is, the nForce3 150 only features an 8-bit uplink running at lower frequency (600 MHz) than the 800 MHz clock, 1600 MHz data rate HT link used by VIA.
It is, therefore, conceivable, that any situation were data need to be written to memory will give the VIA chipset some edge, this includes reads from the hard disk drive as well as any data incoming through the network controller or even data that are coming from the AC97 soft-audio controller. Further downstream, the K8T800 connects through the VMAP interface with the VT8237 South Bridge, the "8x Vlink" interconnect used here boasts a total of 533 MB/sec bandwith.
The VT8237 extends into a number of integrated peripherals from the Vinyl Audio over the Gigabit, USB and Firewire along with what is probably best described as secondary PCI bus and Super I/O Legacy interface (Parallel, Serial and Floppy) to the VIA Drive Station, according to VIA, the first native SATA solution featuring more than RAID 0. To be native or not to be native SATA, that will be here one of the questions, though.
It is important here to understand that the South Bridge - North Bridge interconnect is not the PCI bus but the 533 MB/sec Vlink and that the PCI bus branches off the South Bridge as one of the daughter branches of the Vlink / VMAP data path to the AGP Tunnel and further to the CPU and memory. In theory, the K8T800 chipset supports both single and dual channel memory, which is actually trivial since as mentioned above, the memory interface is no longer a task of the chipset but has been completely relegated to the CPU.
One of the first boards to market using the VIA K8T800 chipset is the ASUS K8V using the Socket754 interface and, consequently, only a single channel memory controller. The predominant features of the K8V are, aside from the Athlon64 support, the presence of two SATA RAID controllers and, finally, the long anticipated wireless module bundled with the "Deluxe" edition.
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