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| AMD Athlon64 3200+ - ASUS K8V Deluxe The Middle Grounds | |
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(Review by MS, November 3, 2003) |
| K8V Deluxe At: |
In Detail
The K8V AMI BIOS features a few settings that are new or at least have not yet trickled down to what could be considered common knowledge. Especially since the manual skimps on most of these settings, here are at least the more unusual parameters:
HT Tristate Enable:
During a LDTStop (LDT: lighting data transport; the original name for HyperTransport) the link can disconnect and go into a "floating" tristate.
CRC Flood Enable:
CRC stands for cyclic redundancy checking. If errors occur in the transmission of CAD data packets, the interface needs to be synchronized again in order to know the begin and end bits of each data packet. This can be done by sending "sync" packets through the HT Link.
HT Frequency:
HT bandwidth depends on frequency and bus width, the K8V allows signaling frequencies of 200-800 MHz clock rate using a DDR protocol for 400 Mbps to 1.6Gbps data rate per pin.
Memclock:
Auto will set the memory clock to the SPD setting, that is DDR333 will run at 333 MHz and so forth, independent of the CPU external clock input. If set to Limit, the memory frequency can be selected manually but there will be an upper limit defined by the module's SPD programming.
Memclock to CPU Ratio:
Only available if the memclock is set to "Limit". Depending on the CPU used, different memory frequency ratios are available from DDR200 to DDR400. Keep in mind that the SPD limitation cannot be exceeded, that is, PC2700 DDR can only run at a maximum frequency of 333 MHz data rate.
Bank Interleaving:
Bank Interleaving allows to keep one page per internal bank open even at different row addresses. With current DDR, this amounts to four open pages per physical bank of memory.
CAS Latency:
Time from a read command until the data are output onto the bus.
tRC:
tRC: Bank cycle time: minimum time between two consecutive bank activate commands to the same physical bank
tRFC:
Auto refresh or CAS Before RAS (CBR). DRAM needs to refresh periodically in order to retain its data which can be done by an internal counter / scheduler and a so-called CBR command. The auto refresh time used to take the same number of cycles as a standard bank cycle, however, with increased DRAM densities, oftentimes now two consecutive rows are refreshed back to back, which takes twice the amount of time. With current DRAM chip densities, this is not yet an issue, however, with the upcoming densities of greater than 1 Gbit/chip, tRFC will have to be roughly 2 x tRC.
tRCD:
RAS-t-CAS delay: time it takes to open a page and latch all bits from the memory cells into the primary sense amplifiers within the memory array. By far the most critical parameter for both stability and performance.
tWR:
Write recovery time. Writes are carried out at a CAS latency of 1T but it takes a few cycles after writing the last bits until the page can be closed, that is, until a precharge command can be issued. This time interval is called "Write Recovery Time" and depends on the frequency. At DDR400, the recommended setting for safe writing without risking data loss is 3T.
tRWT:
Read-to-Write turnaround time. Number of memory cycles after a read until a write can be done without running into bus contention and other issues. We recommend 3 cycles for high quality DDR400
tRAS :
RAS Pulse Width or minimum bank open time: number of memory cycles until a page can be closed by another memory request to a different bank. Keep in mind that the minimum tRAS should not be less than tRCD+ CAS+2 extra cycles for data transfers, anything lower will result in performance degradation since an ongoing read request can be truncated after the first four transfers. Rule of thumb: Higher tRAS => Better performance.
tRP:
Precharge delay, cycles necessary to write back the data from the sense amplifiers to the memory cells when a page is closed. A shorter tRP will give better performance but will be less stable.
Everything else is rather self explanatory except for the "Performance Mode" that appears to do some changes in the overall system timing. We have read on AMDMB that the different "Turbo" modes also change the external CPU frequency, however, we were not able to replicate these findings with either CPUZ or CPUID. There appears to be some Spread Spectrum Modulation that can account for some initial ramping of the CPU clock upon launching of either application, however, within a few seconds, all performance settings settled at exactly 205 MHz external clock input, regardless of whether it was the "Safe", the "Standard" or any of the Turbo Settings.
next page: => Test Configuration =>
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