Navigate:

Advice
Beginners
BIOS Guide
CPUs
Links
Mainboards
Memory
Network
Storage
Video/Sound Cards

Contact
Forum
SiteMap
Sponsors
WebNews
Home
. .

Prices:
CPU
Intel
P4 2.4C-800
P4 2.6C-800
P4 2.8C-800
P4 3.0-800
P4 3.2-800

AMD
AthlonXP
XP 1700+
XP 2000+
XP 2400+
XP 2500+
XP 2700+
XP 3000+
XP 3200+

Athlon64
Athlon64 3200+
Athlon64 FX-51

Opteron
Opteron 240
Opteron 242
Opteron 244
Opteron 246

Memory

Corsair
Crucial
Kingston
Mushkin
OCZ

Search Prices:






















































































What are you
shopping for?



































































































































































LOSTCIRCUITS

SHORTCUTS:
An In-house chipset for AMD
At One Glance
What You Get
Layout and VRM
Integrated Peripherals
BIOS
Test Configuration and Overclocking
Memory Performance
TrueSpace
POVRay
Cinebench 2003
Video Encoding
FarCry
Prey, DOOM3
F.E.A.R.
3DMark
Final Words

Comment in the LostCircuits Forums

 ASUS M2R32 MVP
Clocking like a Banshee
(Review by MS, Dec. 19, 2006)
The Board

Layout

The first thing catching the eye about the M2R32 MVP is the "proprietary Asus" layout with the horizontal arrangement of the memory slots against the upper edge of the motherboard PCB. A similar layout is used on a number of ASUS boards including the M2N32 and it is just as intriguing as it ever was since there is no overlap whatsoever between the memory and the PCIe graphics real estate. Especially in the case of high end crossfire cards, keep-out zones are important considerations given the fact that there are quite a few cards with double-sided coolers / dual slot cooling solutions.

Naturally, the memory slot placement at the top of the PCB shifts the CPU socket a bit down and to the right of where it is usually found. On the other hand, this also allows for a slightly more compact arrangement of the CPU-chipset aggregate, even though, in the days of clock forwarding, the spatial geometry and the trace length in particular is no longer that much of a concern. On the other hand, it is still a trivial issue that longer traces are more susceptible to noise and EMI and that shorter traces are in general considered more overclocking-friendly. We will look in to this a bit more in the following.

           

The expansion slot layout is more or less dictated by the use of the RADEON R580 North Bridge with its support for two 16 x PCIe slots. Because there is no memory in the way and the North Bridge has been moved out to the right hand side of the PCB, there are no constraints that would be in the way of placing the first (master) PEG slot in the top-most position. Similar as in the case of the Sapphire Pure Crossfire AM2RD580 , the two PEG slots are separated by a triple-width spacing. However, in contrast to the Sapphire board, where any Crossfire configuration essentially eliminates the use of any other expansion slot, the ASUS layout is using the potential triple width cooler keep-out for the potentially useless PCIe 1x slots. Even in a current high-end dual slot solution, therefore, at least one standard legacy 32-bit PCI slot remains available.

Bottomline is that the M2R32 MVP layout provides for a very versatile use of the expansion slots with the PCIe 1x slots being the first to be sacrificed in case of a high-end graphics solution which makes perfect sense in view of the pretty much non-existence of suitable cards.

Power connectors, VRM and Clock

The placement of the power connectors is by now pretty standard, that is, the 24-pin extended ATX connector is at the right side of the PCB, just inside of the single IDE connector. The auxiliary 12V connector - in this case a 4 pin connector - is positioned on the left of the PCB, just above the primary PEG slot at the heart of the CPU's voltage regulator module (VRM). The VRM itself is built around the AnalogDevices ADP3186 8-bit programmable 2-4 phase controller IC using three ADP3418K driver chips to interface with three MOSFETs each. A typical MOSFET configuration for this controller uses one high-side and two low side switches for a total of three FETs per phase. This explains the "case of the missing MOSFET" per phase - in other words, nothing is wrong here and it is not an issue with shaving a few extra pennies to have the fourth gate omitted from each phase, rather, it is perfectly within the design specs. Needless to say that the necessary chokes and capacitors are in place for elimination of HF noise and whatever is left of ripple currents. The memory VRM is based on the Anpec PW7120 synchronous buck controller driving two N-channel MOSFETs in a pretty standard configuration.

Schmitt Trigger for Cleaner Clocks

The clock input is generated by the ICS9B24CAFLF clock generator with a positive feedback loop provided by the Philips HC74HC14 Schmitt trigger IC. This type of design is typically used to enhance the quality of a "dirty" input signal with slow rise and fall times into a sharply defined, jitter-free high-speed signal - just what the doctor ordered for overclocking. Needless to say that this IC is as close as possible to the CPU socket, in this case, inside the mounting bracket for the cooler.

next page:    => Integrated Peripherals =>

If you enjoyed reading this article and found it useful, please consider making a small donation to LostCircuits.
Thank you!

General disclaimer: This page only reflects the author's personal opinion and assumes no responsibility whatsoever regarding any of the contents or any damages that may occur explicitly or implicitly from reading the contents of this site. All names and trademarks mentioned in this review are the exclusive property of the respective parent companies.
All contents of this site are protected by international copyright laws. Reproduction of the contents even in parts is not allowed