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LOSTCIRCUITS

SHORTCUTS:
Top Page
Dual Channel vs. TwinBank
Behind the Errata
ASUS P4G8X
Features
Layout, VRM
Connectors etc.
BIOS
Setup / Sandra
Expendable, Winstones
3Dmark, Comanche4, UT2003
ViewPerf
Conclusions

Any Comments?

Find the P4G8X online

 ASUS P4G8X Deluxe    
The Black Obelisk
(Review by MS, December 15, 2002)
Summary

Intel's release of the E7205 Granite Bay chipset for the workstation market has caused the awkward situation that mainboard manufacturers are using the expensive silicon to compete in the desktop space for the crown of the Dual Channel DDR platform for the Pentium4. Demands on workstations differ from demands on desktop PCs with respect to the emphasis on performance and features vs. stability and, therefore, it is not too surprising that the Granite Bay-based desktop boards are comparable to Sports Tractor-Trailers. These considerations aside, we have dug through the data sheets for the bugs and errata, thrown in all possible and impossible memory configurations and looked at how the different parameters affected performance.

The innocent victim of our investigation was the ASUS P4G8X Deluxe, featuring a number of on-board goodies like Gigabit Ethernet and other advanced features supported by the ICH4. So how did ASUS do with implementing the Dual Channel E7205 on a mainboard? Did they manage to get everything to work? Or do we need to wait for Spring(dale) to come?


Memory bandwidth concerns have been the driving force behind Intel moving towards Rambus technology. The latest incarnations of Intel's dual channel 850 chipset with support for PC1066 Rambus did provide more than 4 GB memory bandwidth, which almost exactly matches the bandwidth of the processor bus in the Pentium4. With increasing speed grades of Rambus memory, the major crux of the technology in the form of initial access latencies were ameliorated and the increased performance and granularity, for a short time, suggested a possible comeback of Rambus into the PC platform. However, in retrospect, it appears as if the switches had been set earlier already and even though some of the reasoning at hand was neither performance nor business related but rather played into personal issues, Rambus is out of the picture, at least for now.

Granite Bay Block Diagram. The E7205 MCH's most distinguished features are support for AGP 8X and dual bank DDR memory

The, er, somewhat forced, departure of Rambus, of course, left a huge void in the data access path to the Pentium4. The first generations of DDR chipset as we have the various conceptions of the i845 have been shown to deliver more than adequate performance. However, unlike the AMD Athlon family that is limited by the CPU interface bottleneck, the P4 with its quad pumped bus and a sheer insatiable hunger for bandwidth appears to have the potential for unleashing even more performance with a wider bus. That is, at 533 MHz data rate, the 64 bit wide CPU interface is capable of funneling 4.3 GB/sec data to the processor. In contrast, the Athlon can only do 2.1 and 2.7 GB/sec at 133 or 166 MHz external CPU bus, respectively, regardless of the memory bandwidth. Therefore, a dual channel DDR memory interface will naturally favor the P4 over the Athlon with respect to performance gains since the Athlon platform gains will be limited to simultaneous CPU and DMA accesses whereas the P4 will be able to saturate its bandwidth. The result is the latest Intel chipset a.k.a. E7205 or Granite Bay, a spawn of the E7500 server chipset introduced by Intel at this year's spring IDF.

Dual channel means that standard bus width is doubled from 64 bit to 128 bit data, if the ECC check bits are taken into the equation, the bus width is 144 bit total but for clarity we will refer to the data bus only, which is standard convention in DRAM and interface parlance. A total of 4.3 GB/sec memory bandwidth should be enough to satisfy the AGP interface along with the CPU. Even at AGP 8X and 2.1GB throughput, the remaining 2.1 GB/sec are still what any home-style i845D chipset would maximally deliver to the processor.

Dual Channel DDR, of course, also requires additional data and control pins. Keep in mind that the 72 bit total width of each memory channel also needs 72 data pins (compared to 16 in Rambus), add the extra control and address pins and the E7205 comes up with a record-breaking 1005-pin package in Flip Chip-Ball Grid Array (FC-BGA).

next page:    => Dual Channel vs. Twin Bank? =>

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