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From the nVidia nForce chipsets, we know the concept of the memory TwinBank architecture, where two separate memory controllers in crossbar configuration are interfaced via a single step arbiter that selects the appropriate channel for the CPU-to-memory or DMA channel setup. The arbiter necessarily introduces some additional latencies that have been ameliorated in the second generation, that is the nForce2.

Dual Channel DDR support a la Intel is fundamentally different from nVidia's TwinBank Architecture. In the latter, two independent memory buses are operating, with Intel's solution, two DIMMs are recognized as one single 128 bit wide entity, that is the "ÜberDIMM" meaning that each page that is opened is also 128 bit wide and every transfer will encompass the full bandwidth. In case two different density DIMMs are being used, that is, a single-sided and a double-sided DIMM, the controller can't but ignore the smaller DIMM, otherwise it would have to toggle between 64bit and 128bit transfers and at some point try to write 128 bits into a 64 bit memory space or vice versa. That would leave it confused.

The E7205 memory controller has no need for an arbiter and does not show separate memory controllers in the device manager either. According to the Intel white papers, a memory configuration utilizing both channels (A and B) will be seen by the memory controller as a single bank spanning across both DIMM slots. That is, each row (the term used by Intel) is 128 bit (data) wide. Of course, this causes the problem of how a 128 bit wide burst of data is going to be funneled through a 64 bit interface. Keep in mind, though that the external CPU bus is running at twice the data rate (QDR instead of DDR) and, therefore, the 128 bit data chunk can be split into two 64 bit transactions on back-to-back transfers. Also keep in mind that the utilization of the 128 bit interface will require the presence of two identical DIMMs at least with respect to their configuration. That does not mean that both DIMMs have to be from the same vendor, it is certainly possible to combine DIMMs of similar quality, e.g. a Corsair with an OCZ DIMM, they will be running in DDR266 mode anyway. However, different format DIMMs cannot be run in the complementary channels, that is, if slot A1 is populated with one double-sided 512 MB DIMM and slot B1 with a 256 MB single-sided DIMM, the latter will not be seen by the chipset.

For the record, the E7205 no longer supports DDR modules using x4 components, this particular configuration is mostly used in servers which makes the lack of support somewhat surprising since the E7205 is an offshoot of the E7500 Plumas chipset. We found a way to trick them, though. Officially supported chip widths are x8 and x16 but here is the next conundrum: x16 chips are supported only in single-sided configurations. Since any DIMM using x16 chips can only sport 4 chips per bank, this limits the total density of such a DIMM to 128 MB (using 256 Mbit technology). Using x8 components, there are no specific limitations listed in the data sheet and we'll have more on that later in the review.

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