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LOSTCIRCUITS		SHORTCUTS: Address and CMD Latencies MRO Pipelines P4P800 At One Glance What You Get Layout, VRM Integrated Peripherals BIOS Test Configuration Sandra Memory, Overclocking Cachemem I/O Performance Winstones Gaming Performance Conclusions Flame the author Hot Deals on ASUS boards
ASUS P4P800 Deluxe Springdale on Steroids
(Review by MS, June 7, 2003)

On the first day, Intel created Granite Bay. On the second day, Canterwood, featuring PAT saw the light of the day. On the third day, Springdale appeared. On the fourth day, ASUS came out with a little modification and chaos has reigned since.

The P4P800, based on Intel's i865PE chipset employs a simple, yet very effective trick to bypass the extra pipeline stages in the address and command decode path that ensure stable operation of the Springdale chipset at 200 / 800 MHz frequency. The top yield of the chipset can do without these pipeline stages and the separation between i875 and i865 is a somewhat arbitrarily drawn line between pass and fail under extreme conditions. Therefore the ASUS concept appears only a logical step to break some of the iron "Thou shalt not tamper with our pins" policies.

About 5 years ago, Abit did the same with a switch pulling the B21 pin to ground and everybody overclocked their Celerons happily ever after. Now it is up to ASUS to pull the white rabbit out of the magic hat. We have looked at Intel data sheets and the board itself and ran it through the paces, concerned with speed but also about stability.

What is the technology behind all the chaos? How does the P4P800 live up to the expectations? Moreover, how can it live with the amount of overdecoration ASUS added in form of its Ai feature bundle?

PAT, separating Canterwood from Springdale

The current line of high-end Intel chipset comprises two different lines of chip, that is the i875P and the i865 family. Within the 865 group, the "G revision has a unique position in that it integrates the Intel extreme Graphics2 engine in the core; the 865P and PE versions are the same die as what is sold as Canterwood, using a different package.

Aside from a different package, there are two main differences between the i875 and the 865. First, Canterwood supports ECC whereas Springdale does not, which is the main difference that allows the lower ball count of the Springdale package. Second, Springdale does not support Intel's new performance acceleration technology or "PAT".

So what exactly is PAT. Performance acceleration technology is a means to speed up address and command decoding. Address and command decoding are necessary because the virtual address space created by each software application will attempt to maintain a contiguous memory space. If more applications are running, more contiguous memory spaces will be necessary. PC memory falls into the category of Random Access memory, meaning that data can be written all over the place, depending only on which pages are open at the time that the write command is issued. This resembles pretty much a shotgun approach and, therefore, maintenance of any contiguousness would be a matter of scarce luck unless some extra measures are taken.

These measures are the translation of the physical addresses into a virtual memory space (not to be mistaken with the virtual memory or swapfile in the Windows environment) where every application maintains a contiguous block of memory or at least thinks it does, courtesy of the tags stored within the application address tagRAM more commonly referred to as TLBs, short for Translation Lookaside Buffers on the processor level. The tagged information still needs to be converted into physical memory addresses, which requires some work on the memory controller level. Needless to say that work does require time, which, in this case is called address decode latency. An extra step added is the command decode latency also known as CMD Rate to any users of VIA chipsets.

All these latencies add on top of what is generally known as the DRAM access latencies, where tRAC defines the time from Chip Select to the first or critical Quad-Word output to the bus. Just as a short reminder, the DRAM latencies themselves start with the RAS-to-CAS delay on top of which is added the CAS latency. In case both of those latencies are set to 2, tRAC at a 200 MHz system bus (chipset) frequency would be 4 x 5 ns or 20 ns. However, real world latency measurements show system initial access latencies that are generally in the order of 50-100 ns and encompass all steps from the time the CPU issues the request for the data until the actual data output. At a 200 MHz system bus frequency, the differences translate into some 6-18 chipset clock cycles.

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