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With the P4S333, ASUS fills the void for a high performance P4 DDR board in their repertoire. Using the SIS 645 chipset, the P4S333 offers an extreme of memory bandwidth in streaming applications, courtesy of the 3:5 (FSB:memory) ratio, which allows to run the memory bus at 166 MHz without even overclocking. Compared to the equivalent Soyo Dragon Ultra, the P4S333 is not as fashionable but offers excellent functionality, performance, stability and compatibility, even with the GeForce4. In terms of performance, the high memory bus speed is bought with high latencies that won't affect performance in some streaming applications but will slow down the system in standard applications. Overall, the P4S333 is an extremely high quality board with the potential to bring out the best of any Pentium4 CPU.

Schematic overview of the SIS645 chipset

If we look at the common features of the Intel, ALi and SIS chipset, it really appears as if they all follow a master plan devised to enable a certain performance sector for the P4 platform. At the same time, clipping the wings of the P4 DDR chipsets ensures survival of what Intel describes as "the technology with the highest performance and granularity" a.k.a. Rambus. Our original thought was that SIS would come out earlier with their chipset which would have allowed Intel to use one of their "allies" to committ to DDR technology without violating any Rambus contract. As things turned out, though, Intel beat SIS to the punch with their own i845D chipsets, even though that one is not exactly a rocket (scientist?) among current chipsets.

One example for the above mentioned master plan is the lack of support for any registered DIMMs which poses a ceiling of currently 1GB system memory for the i845D and ALi chipset and 1.5 GB with certain caveats for the SIS 645. ECC is not supported either in any of the above mentioned platforms. Likewise the IOQ Depth is 12 levels in both the Brookdale and the SIS 645 controller. While these features or their omission can be explained by market demands, there are some other tell-tale signs about the crib of the SIS 645 chipset. Take the use of dynamic bus inversion or DBI, which is just a little bit too fancy to allow for any explanation based on coincidence.

What Again Was DBI?

From our original Brookdale review, here is a quote:

Dynamic Bus Inversion

Multiple data lines firing all at once can cause unwanted electrical noise at the controller and the processor. Dynamic bus inversion (DBI) provides a rather interesting feature that allows inversion of signals in order to avoid electrical noise caused by Simultaneous Switching Outputs or SSO. The fact that the outputs all switch at once is not necessarily the problem. In fact, if the pattern 10101010 were then followed by 01010101, everything is just great since the bits balance each other out. Rather, large noise spikes are created when lots of data pins switch to the same polarity, with the exception of one (or a few). Even in this case, there is only a problem if the majority of lines switch from high to low since in this case a phenomenon known as ground-bouncing can happen. The problem can be completely avoided if an extra line DB#1 is added to each 16 data lines.

As mentioned, the problem arises only if more than 50% of the data lines simultaneously switch from high to low. This "mass switching" can be completely avoided if the Dynamic Bus Inversion line is switched instead of the actual data lines, as long as both ends of the data bus know that the "reference line" is switched instead of the actual data lines. The most striking example would be a simultaneous switch of all data lines from 1 to 0 which is the worst case scenario for SSO noise. With DBI, all data lines can stay high and only the DBI line switches polarity, thus providing an indirect or substitute signal for the switching of the data lines. ...

For most users, however, the SIS 645 chipset is not characterized by DBI but rather by its capability of running the front side bus / memory bus in a 3:4, 2:3, 3:5 or even 3:6 ratio. In plain English, this means that while the CPU is running at 100 MHz FSB (clock speed), the memory bus can be running at an arbitrary frequency, most commonly at multiples of the PCI bus frequency, that is either 100, 133, 150, 166 or 200 MHz. In most cases, the 200 MHz memory speed cannot not really be considered a viable option (certainly not from a marketing point of view), however, the 166 MHz memory bus has become something like the trademark of the SIS 645 chipset, hence the 333 suffix in the name of some mainboards. A case in point is the ASUS P4S333.

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