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LOSTCIRCUITS		SHORTCUTS: 6.4 GB and Now What? Separating the DMAs Solving Speed Issues Performance Acceleration Technology A few new Silicons Bonanza Test Setup Memory Performance RAID performance I RAID performance II Winstones 3D Gaming OpenGL / CAD Conclusion Your comments? Intel Mainboards Online
Intel i875 - Canterwood    SATA and GbE for PAT
(Review by MS, April 14, 2003)

One issue we briefly touched above, concerned the differences in system memory configurations. More precisely, both single and dual channel modes are allowed and as long as the module configuration in each complimentary slot is the same, the two modules can be combined to work in dual channel operation. It is, however, quite an ordeal to keep all parameters under control, especially when moving on to a high-speed solution like DDR400. To accommodate all variables, Intel is using what they call "advanced design for DDR400 speeds" which circumscribes mostly three different strategies:

• Self compensating drivers eliminate fluctuations caused by PVT variation:

  PVT stands for process, voltage and temperature and variations of the two latter constantly occur as a function of the operation conditions including seasonal fluctuations or the weather (temperature). Process variations are a function of the different DRAM vendors, e.g. Micron would use a different process than Nanya or Winbond and Samsung would be different from Infineon. All these parameters need to be compensated for in order to warrant flawless DDR400 operation, Intel-style, which means under all circumstances. Self-compensating drivers adjust for the variability in design and operating conditions, that is, the drivers can self-adjust the drive strength to allow a precision tuning of the controller - DRAM interaction without user intervention being required. Likewise, the drivers will be able to adjust for different load caused by higher or lower system memory density.

• Adjustable Clock outputs enable clock adjustments based on DIMM population:

  Having four slots on-board will cause different levels of trace delay between the individual slots and the controller. Especially in the case of dual channel operation, however, it is necessary to synchronize all signals as closely as possible. Since the DRAM in DDR is not running on the system clock per se but uses a clock-forwarding scheme based on the I/O strobes, there is a possibility to individually adjust these output clocks according to the population scheme in the system. That is, if slots #1 and #4 are populated, a bubble or delay will be inserted into the clock to even out timing differences between the slots at both ends of the spectrum.

• Managed receiver termination improves signal quality during high-speed transactions:

  Termination of signals is an extremely important parameter to avoid collision of reflections and real signals and, thus, ensure signal integrity. Since DDR-I does not yet accommodate for on-die-termination (ODT), termination still needs to be done on the receiver / mainboard level. Managed Receiver Termination is another buzzword to imply an adaptable scheme for signal termination depending on strength and origin. Most likely, programmable, variable resistance of the ground strap is used to provide optimal elimination of ringing and similar artifacts.

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