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LOSTCIRCUITS		SHORTCUTS: 6.4 GB and Now What? Separating the DMAs Solving Speed Issues Performance Acceleration Technology A few new Silicons Bonanza Test Setup Memory Performance RAID performance I RAID performance II Winstones 3D Gaming OpenGL / CAD Conclusion Your comments? Intel Mainboards Online
Intel i875 - Canterwood    SATA and GbE for PAT
(Review by MS, April 14, 2003)

The main thing setting AMD's Hammer family apart from any conventional system is the integration of the memory controller into the processor with the desired effect of using shorter cycles (shorter processor clock than chipset clock) to decode addresses and commands before the actual memory array is accessed. Briefly, modern operating systems and applications are using virtual memory addresses rather than physical addresses, meaning that even data randomly distributed across the physical memory address space will be seen by the OS as forming one single contiguous block. A classical example is the AGP aperture that, by definition, needs to be one contiguous block, which however, is formed virtually by the use of the graphics allocation routing table or GART.

One clock cycle was shaved off each from the address decoding and the actual command decoding to allow the chipselect to be done two cycles earlier than on Springdale.

All programs are using similar virtual memory space, the tags for which are stored inside the translation lookaside buffers or TLBs. Needless to say that the virtual addresses must be translated into physical addresses. Likewise, the chipset needs to know whether it is a read or write or precharge command that is given to the relevant address before the physical bank is selected by pulling chip select (CS) low for a logical true. The time taken to complete these tasks is the so-called address and command decode latency commonly referred to as CMD-rate.

In single channel memory configurations, running at lower chipset frequency, it is not a big problem to run at a reduced CMD rate of 1T. Ramping up the chipset / memory controller frequency to 200 MHz arguably makes things a bit more difficult, despite all preventive measures taken as outlined above. Currently only the top bin of the chipset silicon is capable of performing reliably at this speed which means that only Canterwood will be capable of using this new Gelsinger icon.

Aside from Canterwood, the other chipsets that were censored here will not feature PAT.

Not supported by the non-i875 dual channel solutions is ECC which arguably has no value for the consumer desktop anyway.

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