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LOSTCIRCUITS		SHORTCUTS: 6.4 GB and Now What? Separating the DMAs Solving Speed Issues Performance Acceleration Technology A few new Silicons Bonanza Test Setup Memory Performance RAID performance I RAID performance II Winstones 3D Gaming OpenGL / CAD Conclusion Your comments? Intel Mainboards Online
Intel i875 - Canterwood    SATA and GbE for PAT
(Review by MS, April 14, 2003)

Any new chipset usually comes with a new package with differences in the pin layout and count. We have seen the staggered ball array already in the i845 chipset family and the 7205 a.k.a. Granite Bay, as a means to facilitate manufacturing on reduced-layer PCBs. What is not clear is the ball count of the new MCH. The i845PE chipset uses 593 balls, the i845G uses 760 pins, Granite Bay is using 1005 balls and we have some marketing numbers from Intel that do not match the data sheets. The only thing that appears clear at this point is that the package size has not changed from the currently used 37.5mm (edge length) square. The die size is ca. 85mm², a sizable chunk of silicon using flip chip technology.

The new ICH5 or i82801EB features dual independent SATA controllers which is sort of the equivalent of the dual independent channel IDE controller. In other words, rather than splitting the bandwidth to each port via a port multiplier, both of the two ports shown on the right is mapped to its own controller via point-to-point topology for uninterrupted data exchange.

The last IC worth mentioning is Intel's new Gigabit Ethernet controller enabled by the Intel 82547EI controller. Connecting the controller directly to the MCH via a 266 MBs dedicated connection dubbed CSA for communication streaming architecture.

Nested amid the supporting filters and status LEDs is the 82547EI Gigabit Ethernet controller. Since the data are going directly through the MCH to memory and then to the ICH via the HubLink, there is no bus contention that could cause latencies in the data traffic.

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