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LOSTCIRCUITS	SHORTCUTS: Top Page Mobile Specs The DFI 855GME-MGF Test Configurations Memory Performance WorldBench5 Sysmark2004 3ds max Amporphium3, Lightwork, Cinebench Cinebench2003 Realtime Gaming Performance Final Words Your Comments Can Help Us Improve Our Reviews
DFI 855GME-MGF and Intel Pentium M 735 Along came a Dothan
(Review by MS, Jan 2, 2005)

Realistically viewed, the appearance of the PentiumM in the desktop world is not totally unexpected. RadiSys, based in convenient proximity to Intel’s Hillsboro, OR location has had the Endura LS855 µATX board for quite some time in their repertoire as a low power server backbone alternative, using the 855 chipset in combination with Intel’s 6300ESB southbridge. This combination is typically employed in embedded solutions. The 6300ESB is interchangeable with the ICH4 in terms of the interconnect, however, adds native support for SATA 1.5 to the system logic. Keep in mind though that the SATA support of the 6300 ESB only encompasses the first generation of specifications and features, meaning that there is no support for native command queuing or the advanced host controller interface with its hot-plug and advanced power management features.

On the other hand, the 6300ESB does support PCI-X64/66 and PCI 32/33, which at least offers the possibility to attach some more sophisticated mass storage controllers. Keep in mind, however, that the 8-bit hublink 1.5 can only support 266 MB/sec of total traffic, which is not even enough to fully support the PCI-X interface used. Anyway, the 6300 ESB is the most advanced I/O solution compatible with the 855 chipset and as such it has to suffice. Keep in mind that we are working with such outdated specifications as DDR333 and AGP4X here, which, as we all have learned in the past few weeks are archaic technology at best.

One of the technology partners listed on Intel’s developer site is DFI, short for Diamond Flower Int. Among all the major mainboard manufacturers, DFI is the only one currently supplying a mainboard based on the 855 chipset. We do have some information that similar efforts are underway at ASUS, Shuttle and other manufacturers, even though the choice of chipset may be different in that a mobile version of the 915 chipset may come into play to extend the feature repertoire to PCIe and SATA 2. Whether this will make a difference or not – we’ll see when the time comes.

   

Intels 82855GM GMCH and the 6300ES I/O controller hub form the core logic of the DFI 855GME-MGF

The CPU

The mobile Pentium-M uses a similar interface as the classic Socket 478 Pentium4. Keep in mind that despite the similarities between the physical layout of the Pentium-M and the Pentium4, electrically, the Pentium M is not compatible with e.g. the 875 chipset or any other Socket 478 interface, neither is the opposite possible, since the pin assignments are totally different. In other words, inserting a socket 478 processor like e.g. a Pentium 4-M into a socket 479 mainboard will most likely end with the demise of both.

With respect to the internal organization of the Pentium-M, Intel has not released much information, other than some IDF presentations from a few years back. Essentially, the Pentium-M is a Pentium 3 on steroids, meaning that the architecture is almost unaltered from the original P6 core design, however, it was transposed to the latest process technology, that is, 90 nm copper interconnect.

The main difference to the Pentium3 is the quad pumped I/O interface or processor side bus, running at 400 MHz data rate to deliver a bandwidth of 3.2 GBs over the 64 bit wide interface. Most notebooks using the Pentium-M use the Enhanced Speedstep Technology to allow dynamic scaling of the PSB to e.g. 533 MHz along with multiplier and voltage adjustments for optimal scalability of power and performance depending on load. The Pentium-M takes things a few steps further in that load-dependent clock gating is used to shut off the clock input to areas of the CPU that are not in use at any given time. This primarily affects the data, control and address signal buffers. Further improvements towards power saving are the dynamic disabling of the on-die termination to avoid passive power draw during idle states, one of the main pitfalls of DDR2 in terms of power consumption. With regard to performance improvements, the Pentium-M has come a long way since the days of the PIII with enhancements in the feature sets including:

• 90 nm Strained Silicon Process Technology
• on-die 32 kB Instruction cache and 32 kB write-back data cache
• on-die 1 (2) MB Level2 cache (8 way set associative) with Advanced Transfer Cache Architecture for transfers on each clock cycle
• Streaming SIMD Extensions 2
• MMX instructions
• Memory cacheability up to 4 GB addressable memory space *

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