LOSTCIRCUITS

Ever since its release, the Pentium4 has been tied to the Rambus memory technology. This symbiotic relationship, even though there were some contract issues involved, somehow makes perfectly sense because of the extra deep, that is 20 stage pipelines of the Pentium4, providing optimal performance in situations of page hits that should have been warranted by optimized branch prediction algorithms. The multibank architecture of Rambus appears, at least at first glance, to constitute the optimal counterpart for this architecture in the broadest sense of the word in that with several open banks, the probability of valid memory requests falling into one of the open banks should, theoretically be rather high.

Intel representatives not long ago claimed an average of 83% page hits in standard desktop applications. This certainly would favor any high-speed interface over any other memory architecture with lower bandwidth, even if there were relatively high initial latencies involved. The word latencies, to spell it out, encompasses any penalty cycle from the issuing of a data request until the critical word reaches the core logic (chipset) to be made available to the CPU. At this point, a different latency in the shape of the front side bus (FSB) is still encountered. However, at least here, with the i850 dual channel Rambus chipset, Intel has taken any possible precaution with its quad pumped 100 MHz interface between the chipset and the CPU, providing a total of no less than 3.2 GB/sec data bandwidth. Seamless data flow from the memory to the ALU and FPU units of the CPU is enabled by an 8 level deep In Order Queue and the CPU internal 20 stage pipeline.

All of this makes perfectly sense in a perfect world where data are stored in memory in logical blocks and where there are no random accesses. Unfortunately, though, the world is not perfect and, even though there are some applications that use a high locality or order of data storage, the majority of application uses random memory accesses. In other words, even the best branch prediction cannot overcome the chaos of any Microsoft operating system. The operating system is, however, only one culprit, more severely, the page hit probabilities are obliterated by the cache architecture of the CPU itself since whatever data are needed or anticipated are prefetched and written back to the L2 cache for faster access in the future. This effectively leads to a time expiration of the page unless non-recurrent data are requested in streaming applications.

Because the performance of both the P4 and Rambus memory technology strongly depends on a logical order of data and requests, all above mentioned performance enhancements would backfire if there were a situation in which the equilibrium is disturbed. It is really very simple, include a page miss or a mis-prediction and the entire elaborate card house needs to be torn down and rebuilt to get back on track. In real life, this includes flushing of the CPU pipelines (20 CPU penalty cycles) as well as closing memory pages and opening the appropriate ones. This situation is exactly the nemesis of both the P4 and Rambus memory but unfortunately for both, this is the most common situation in day-to-day computing. To add numbers to theories, according to some other data published by Intel, page hits make up about 25-30% of all requests in desktop applications. According to some other numbers from IBM and Intel's server group, in server application accesses are totally random, meaning below 2% page hits.

The paradox of mis-prediction of page hit probability by Intel application analysts and the unfitness of the resulting P4 / Rambus combination in the average computing environment, paired with a hefty price tag for RDRAM (Rambus DRAM) and additional concerns about power consumption / heat dissipation by the memory modules has been debated for the last two years. Counterintuitive to technical reasons were financial considerations as well as pending legal issues about patent rights concerning DRAM technology. From the point of view of Intel, there is hardly any other route that can be taken at this time since rumor has it that the Rambus contract could potentially penalize even participation of Intel in DDR roadmap discussions with the proud sum of $500,000,000.00, enough money to have everybody shut their mouth. There is hardly any other way to explain the consistent endorsement and subsidizing of RDRAM by Intel, other than that there were no other alternatives.

Trying to paint a somewhat objective picture here, it needs to be stated that there are applications where the Pentium4 / RDRAM combination proved to be a very valid technical solution. In streaming applications such as video encoding or games with optimized engines like Quake3 Arena, the Pentium4 running on the Intel i850 with its dual channel RDRAM interface has consistently broken any performance records. Nonetheless, in the majority of application, the performance of the above combination has greatly been hampered by latencies stemming from the packetizing protocol needed to funnel 64 bit data through a 16 bit bus and the necessary recombining to a valid 64 bit data set before sending the entire package through the front side bus to the CPU.

Brookdale

The Pentium4 (478 pin) and its SDRAM platform i845, a.k.a. "Brookdale", courtesy of Intel Pressroom

In an environment dominated by political reasons just as much as by technical considerations, it comes as no surprise that the lost legal battles have not only weakened Rambus' pockets but also given Intel the opportunity for a major turnaround of the roadmap. At the Spring IDF, Louis Burns, Vice President at Intel still proclaimed Rambus technology to take over the desktop market by the end of this year, now, in a press release Mr. Burns states:

I fully expect that this (the i845 chipset) will become the next high-volume mainstream platform for IT departments worldwide".

Time to introduce the i845 or Brookdale chipset featuring both SDRAM and DDR controller. Once again, legalism strikes and for the next few months, the DDR part of the chipset, that is data strobe and a few other minor details are disabled. Consequently, we are looking at the SDRAM version of the chipset only.

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