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Brookdale in Detail

In general, the chipset follows the traditional Intel Hub architecture with a memory controller hub (MCH) connected to the I/O controller hub (ICH) via a 266MB/sec high speed interface to warrant enough bandwidth to satisfy simultaneous access of 2 IDE channels and concomitant PCI or other daughter device usage

Summary Diagram of the Intel i845 "Brookdale" SDRAM chipset. Breaking the memory limitations of the i815 chipset, Brookdale supports up to 3 x 1 GB unbuffered non-registered DIMMs. Registered DIMMs are not supported by the chipset, putting an effective limitation of 7698 MB system memory in place at the current state of SDRAM technology. A 266 MB/sec Hub interconnect bandwidth doubles the possible throughput of the older PCI bus which is now a branch-off of theI/O controller hub ICH.

Regardless of whether one likes Intel or not, the technology has always been at the very forefront. Therefore, it isn't any surprise either that the new Brookdale chipset does not feature just the average garden variety SDRAM controller but, in fact, goes a few extra miles.

The two most interesting features of the new memory controller are somewhat related, that is, the controller uses the open page policy already known from the i815 chipset with the option of leaving the pages open indefinitely. In contrast to the i815 MCH, however, the i845 MCH allows simultaneous keeping open of as much as 24 pages, thereby increasing the probability of a request coming back to the same page at some point. Keep in mind that the 24 open pages are a blanco statement for the entire memory architecture, that is 3 DIMM slots with 2 physical banks each or, to rephrase it, each bank can only keep 4 pages open at the time. Thus, while in theory, 24 open pages look very appealing, in practice, one needs to consider that:

• the number of open pages depends on how many banks are populated (only 4 pages / bank).
• each page is one row of memory
• each bank of memory can hold up to 2048 rows (16M parts).

The drawback of keeping a page open over an extended period of time, however, is that a page miss will cause additional penalty cycles because the open pages need to be closed first before even a bank activate command can be issued which opens a new page. Aside from that, there are further temporal considerations, since every page will expire after a certain time, simply because the operations of the system have moved on. An additional problem is found in the form of the necessary refresh cycles. Since DRAM cells lose the data because of leakage currents, each cell's content needs to be refreshed within certain intervals. The protocol used by the i845 controller is the old CAS-before-RAS (CBR), that is a complete read cycle is executed for each row, meaning, the data are read out into the sense amplifiers and then restored to the cell of origin after satisfying the RAS pulse width. There are different ways though, by which the scheduling of a refresh can be accomplished. The easiest possibility is to just move up or down the row decoder in ascending or descending order and have each row do its thing. A different approach is to use a refresh queue and do a burst refresh of several rows at a time. Intel is using yet a different approach called flexible memory refresh, meaning, there is a dynamic scheduling by means of which the refresh of open pages can be postponed if there is a probability that the data might still be requested.

Those scheduling issues aside, open pages are no good if there are no chipset buffers that can hold the data. Intel took care of this issue by adding a 12 level deep in order queue (IOQ) so that data from different open pages can be read consecutively into the pipeline. What it comes down to is the possibility of funneling 12 consecutive 64 bit reads to the CPU.

Internally, the amount of data needs to be made accessible to the CPU using the quad pumped FSB with its virtual 400 MHz operating frequency and the easy way to accomplish it is to increase bandwidth four-fold by means of widening the data path to 256 bit (internally). Other features of the chipset are old acquaintances like the write buffer. Only 5% of the entire memory traffic are writes, however, a single bit write can interrupt a burst read and, thus, it is much better to collect these individual writes and write them whenever there is a gap in the read sequence.

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