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| Shuttle SB61G2 "Spring(dale)-Loaded" | ||
| (Review by MS, May 27, 2003) |
Cachemem
Cachemem is a utility that measures access latencies of block transfers of exponential size across a regular address pattern described as strides. Transfers of small blocks that fit into either the L1 or the L2 cache are rather consistent from one run to another, however, once the main memory is accessed there is quite a bit of variability between individual runs, most likely for the simple reason of memory fragmentation.
It is possible to arbitratily define one specific transfer block size and one specific stride width and use those data but the results will reflect a great deal of randomness and are not necessarily representative for the overall chipset or memory latencies. The correct way would be to use a predefined matrix within the memory array and average all data points therein to get a larger sample that is statistically sound. It is a bit of work that is required for that, though.
SiSoft Sandra2003 Memory Bandwidth
Cachemem scores (lower is better) of the SB61G2 using the Tachyon compared to the Canterwood-based D875PBZ. As long as the transfered blocks fit into the processor cache, latencies for both systems are virtually indistiguishable. However, this changes quite dramatically as soon as the transfer size necessitates access of the main memory. The pigeon-grey blocks are the latencies in ns for the Canterwood, the clear blocks on top show the latency overhead of the i865(x) chipset caused by the omission of performance acceleration technology. Wherever the black and white edges of the blocks are overlaying, courtesy of no difference in latencies, the horizontal edges are grey, wherever there were differences, they show up as black and white pattern.
Please also note the "jagged" surface of both plots which is why we don't believe in random samples at any predefined X-Y coordinate, however reasonable they may appear.
The randomness of the samples gets worse if two sets of data are compared with each other. For illustration purposes, we ran the SB61G2 using the Tachyon G9700 Pro vs. the integrated graphics.
Latency overhead caused by the integrated graphics, everything else being identical. The overhead is caused by the memory controller having to access the display cache for a screen refresh "even while the test is in progress. Keep in mind that the entire main memory matrix should be elevated, as far as we are concerned, the peaks and gaps are artifacts since on the one system the scores just happened to be at the upper end, whereas the opposite happened on the other system. Transfers fitting into the cache show the expected zero difference.
Playing the latency game..
All we did was to change the latency on the system running the Tachyon G9700 to 2:2:2. There is a certain similarity between the this and the above pattern but keep in mind that the base matrix used for the integrated graphics was the same and, therefore, those similarities are neither by chance nor intended but unavoidable.
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