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LOSTCIRCUITS

SHORTCUTS:
Top Page
The FS40 inside
Features, Chipset Overview
Board Details
BIOS and Issues
The Case and the Cooler
Cables, Powersupply
Test Configuration, Squeezing Voodoo
2D, SiSoft Memory and Cache
HDTach, Winstones
Gaming Performance
Illusions of Grandeur
Best Online Prices for Shuttle Products
 Shuttle SS40    
A Cult Is Born
(Review by MS, July 8, 2002)
BIOS

The BIOS for the FS40 is supplied by Phoenix Award and uses the standard yellow on blue interface. Most of the settings are straightforward, that is, everything that concerns the system configuration from the boot sequence to the integrated peripherals and hardware monitoring falls into the "off the shelf" category.

The BIOS does not offer any overclocking settings, but allows adjustments for the different flavors of 100 / 133 MHz FSB CPUs as well as PC1600 / 2100 memory in any combination of the two parameters. Since there are no FSB adjustments and the system is thermally already pushing its envelope it is a wise decision not to add any voltage adjustments.

The DRAM timing settings are somewhat meager, offering Safe, Normal, Fast and Ultra Mode for Auto Configuration. In addition, the CAS latency can be set to 2, 2.5 and 3 cycles, the CPU / DRAM clock synchronization control can be set to either auto, synchronous or asynchronous, meaning that the two clock signals will be derived either from a single clock or generated individually by the two separate clock generators.

Keep in mind that CAS latencies require the equivalent pipeline stages in the DDR chip output path and most current PC2100 chips do not support the CAS-3 option. Setting the system to CAS-3, therefore, will cause failure to POST in most cases since the CMOS will try to force invalid mode register settings on the DDR chips.

The only way out is to open the case and reset the CMOS to default values.

Another issue is that by default, the CPU is recognized as 100 MHz FSB. The potential problem with this is that if the CPU/DRAM synch is set to to Synchronous while using PC2100 memory and without adjusting the FSB to 133, the system will not initialize either. Open the case again and clear another CMOS.... !

The two other settings are:

  • DRAM Background cycles which appears synonymous for the address command decode latency (CMD Rate)
  • LD-Off DRAM RD/WR Cycles which is otherwise known as fast RW turnaround or bus latency.

In the Advanced DRAM CTL 2 menu we have two more settings to specify the chip select and data I/O hold times and those can be critical with certain DDR modules as they are the DDR equivalent of the infamous DRAM Read Latch Delay setting of the ASUS Apollo 133A and KT chipset-based boards. Bottom line here is that with higher density DIMMs, especially 2.5:3:3 rated modules in 2 DIMM configuration, increasing the delay to 1.5 ns may add stability. I don't have any of these modules around so I couldn't test the validity of this hypothesis in this particular configuration but since it has worked in the past, it should be worth a try if things become unstable.

SIS 301 Display Type

A few other goodies are hidden in the second and third order pages, for example, the overall video-out configuration can be custom-tailored for the specific setup used in the SIS 301 Display type submenu of the Integrated Peripherals / SIS OnChip PCI device. Possible settings range from CRT only to CRT + S-V NTSC OTV with options for PAL instead of NTSC A-V instead of SV and OTV instead of UTV in any combination conceivable.

The same submenu also contains the PCI audio device a.k.a. CMedia 8738 6-channel

next page:    => FS40 => SS40 =>

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