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| Tyan Tiger MP (S2460) SMP on a Budget | ||
| (Review by MS, Sept. 23, 2001) |
Summary
Tyan has released the S2460 "Tiger" as the budget version of the S2642 "Thunder" based on the AMD 762MP chipset. Stripped of the integrated graphics, network, SCSI and RAID, the Tiger still preserves all performance characteristics of the high-end server Thunder but recombines the essentials to an inexpensive ATX desktop workstation board. Features include dual Socket A, support for both registered ECC and standard unbuffered PC2100 DDR SDRAM, four 64 bit PCI slots in addition to two more standard PCI slots. System memory is supported up to a total of 3.5GB when registered ECC modules are used, with unbuffered non-ECC memory, the system limitation appears to be 512 MB using DIMMs in a 2x16Mx8 configuration. For around US$200 for the mainboard and some extra change for two SSE enabled AMD CPUs (AthlonMP or Morgan-based Duron), the price performance ratio of a Tiger-based system is probably unmatched for any workstation. A minimum of 400W power supply is suggested, though and the real estate of the case should be measured carefully before jumping into the SMP adventure.
SMP Platforms 1.01
The multiprocessor platform has always been a privilege of a few who were either using exotic operating systems like Unix or else were willing to cope with Windows NT with all its little quirks. Aside from the price tag for a second CPU, the lack of support for simultaneous multiprocessor (SMP) utilization in the mainstream Microsoft operating systems were reason enough for the average user to stay away from any MP Platform.
SMP systems have been around for quite awhile, the Pentium Pro, the PentiumII /III and even the modified Celeron have provided affordable mainstream platforms if anybody needed the additional horse power of the second CPU. Counterproductive for the SMP movement has been the fact that the power of any individual CPU has increased on schedule with Moore's law. Because of the higher clock speed achieved with each generation, single processor-based systems have been able to beat Dual CPU platforms after only a few months.
Intel Dual Solutions and the Problem of the Shared Bus
One additional problem associated with most SMP systems is that the memory and front side bus bottlenecks that effectively hold back today's systems is even worse in SMP systems using the shared bus. The simple math of taking the 800 or 1060 MB/sec frontside bus bandwidth of the GTL+ FSB and dividing it by 2 is an oversimplification that holds only under conditions of 100% bus saturation. In this case, each processor is stuck with ½ of the FSB bandwidth only, however, these conditions basically never occur in real life situations. Short term traffic jams can be compensated for by buffers in the chipset. Regardless of these words of consolation, the inherent problem of GTL(+) based systems not only persists but gets worse with every increase in CPU clock speed.
The typical configuration of a shared bus protocol in which all CPUs share the bus to the controll logic. Because of the shared nature of this approach, the FSB bandwidth of each CPU is divided by the number of CPUs present in real life situations, this equation doesn't hold up exactly since idle cycles of the bus can be used to increase bandwidth to any CPU that is active at the time.
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