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Summary

After entering the DDR chipset market with a re-spin of the KT133 chipset, VIA has taken some heat for lacking performance. Though still faster than the SDRAM chipset, the original KT266 chipset proved marginally slower than competing products from AMD and SIS. The addition of buffer depth and the consequent capability to enable burst length of 8 quad words of data has paid off with an average of 70% enhanced memory bandwidth of the KT266A over the original KT266. The increased memory bandwidth of the new revision gives the entire system a healthy boost of about 10% on a system performance level and makes the KT266A the currently fastest DDR chipset on the market.

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VIA KT266A

Earlier this morning the NDA on the new VIA DDR chipset, model number KT266A and dubbed Enhanced KT266 chipset expired. Hopes are that the new chipset will secure VIA's dominating role in the chipset market by adding performance and reliability over the previous revision of the DDR chipset, the KT266 as we all know it.

The heart of the VIA KT266A chipset is the revamped VT8366 North Bridge

While not a bad performer at all, the criticism has been that there was relatively little performance gain over the standard KT133A chipset, at least at CPU clock speeds below 1 GHz. Therefore, there wasn't really too much of an incentive to move towards DDR. Furthermore, the VIA KT266 chipset was outperformed by most competitors, namely the AMD760 and the SIS735 chipsets, at least in terms of memory bandwidth. On the other hand, the KT266 chipset could be positioned between the AMD 760 and the SIS735 chipset in terms of the interconnect between the memory and AGP controller (North Bridge) and the I/O controller (South Bridge) which features the VIA VLink offering 266 MB/sec bandwidth. As a reminder, the AMD chipset is still using the PCI bus as interconnect and is, therefore, restricted to 133 MB/sec. The SIS735 chipset on the other hand uses the MuTIOL 8-channel interconnect with a possible bandwidth of 1.06 GB/sec which, at least in multi drive configurations provides a substantial performance increase.

The relatively modest performance of the VIA KT266 chipset can be understood quite easily when looking at the memory controller. The chipset itself is a re-spin of the KT chipset and as such has not undergone too many architectural changes. Of course, features absolutely necessary for the accommodation of DDR such as the DQM (data strobe) had to be implemented but that was as far as most of the changes went. What was missing from the original KT266 chipset were some features that are absolutely necessary to unleash the power of DDR.

About one year ago Kyle Bennett on HardOCP and I stuck our heads together for an article on performance issues related to DDR and future DRAM architectures, including a theoretical analysis and prediction of memory bandwidth. Based on statistical numbers on page hit vs. page miss occurrence we calculated the performance of DDR vs. SDRAM under different controller implementations. As it turned out, the one crucial factor on which the average bandwidth depended was the burst length programmed into the controller.

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