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A quick review of IOQ and burst length in SDRAM

Most SDRAM controllers are using a burst of 4 words in consecutive memory clock cycles, however, in order to take advantage of a burst, the controller needs a buffer to hold the data. Since the buffer cannot reschedule the transfers it is commonly referred to as in-order-queue and its depth is given in levels. In other words, the pipelined burst length depends on the depth of the buffers. As of the VIA 694X chipset, all VIA chipsets feature a 4 level IOQ and that limits the burst to 4 words.

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The IOQ and burst length in DDR-SDRAM

DDR is capable of data transfer on both the rising and the falling edge of the clock which means that a burst of 4 is accomplished in 2 bus cycles. From a controller design standpoint, it appears easier to stick with the established 4 cycles of data transfer after a read command and increase the burst length to eight transfers. This is exactly what AMD has done in their 761 North Bridge, likewise, ALi did the same in the MAGiK1 (I have no data available on the SIS controller, though). However, as stated above, the fact that the KT266 as a re-spin of the KT133A chipset only featured an IOQ of 4 level depth did not allow to increase the burst length which put VIA in a rather unique situation in the DDR world.

Adding the missing IOQ levels as key to performance

The major change from the KT266 to the KT266A chipset is the addition of additional data buffers, that is, the IOQ has been increased to a depth of 8 levels. This, in turn, allows VIA to increase the burst length to 8 words which should have a substantial impact on the overall performance.

Overview of the VIA KT266A chipset as taken from the VIA white papers

Other key features include AGP4X, ATA-100, and PC133 support, as well as integrated six channel advanced audio, six USB ports, LPC bus, and integrated 10/100Mbps Ethernet and Home PNA, AC-97 audio, MC-97 modem, and support for AMD's second generation PowerNow! technology.

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