Key event of IDF Spring 2002 was without doubt the unveiling of Intel's new Server chipset E7500, codename Plumas to fully endorse the migration from SDRAM to DDR. The move to DDR is a 180 degree turnaround from last year's Spring IDF memory roadmap where Intel still maintained SDRAM as the most suitable memory platform for servers since the superior technology of Rambus would be wasted on this platform (read: "the initial access latencies of Rambus lead to detrimental performance degradation in the random access environment of a server platform"). It is a logical step for Intel to endorse DDR now since gagging by the Rambus contract is a thing of the past. Moreover, it makes sense to consolidate the desktop and server memory platforms to one common architecture. The renewed presence of Intel at JEDEC in the past few months and their ramped up participation in DDR specification are the best indication for the long anticipated dawn of the post-Rambus era.

I7500 Chipset Overview
(picture courtesy of Intel)

Unlike the standard Intel hub architecture with its serial order, the E7500 arbors out in parallel branches from the E7500 Memory Controller Hub (MCH) towards the 82801CA I/O Controller Hub 3-S through a Point-to-point Hub Interface HubLlink (HL) 1.5 connection as well as to up to three 64-bit PCI/PCI-X Controller Hubs (P64H2) via an HL 2.0 connection. Interesting here is that Intel is still using the shared FSB, however, with a quad-pumped interface delivering 3.2 GB/s bandwidth with the option of scaling up to 4.26 GB/sec once the 133 MHz bus clock is implemented, it appears save for the time being and the near future

Briefly, the E7500 supports dual Xeon processors and further contains a dual channel DDR memory controller with support for 16 DIMM slots of 2 GB density each. The memory bus runs synchronous with the FSB, meaning that only PC1600 is supported. At first glance this appears somewhat backwards, however, keep in mind that servers do not require high peak bandwidth that is useful only in data streams but rather need low access latencies. An asynchronous memory bus running at e.g. 133 MHz would provide higher peak bandwidth (rather useless in server applications) but would have the drawback of needing fifos and synchronizers, which, in turn, would add latencies to the memory bus. From this standpoint Intel's decision to stick with the nominally slower 100 MHz PC1600 interface makes perfectly sense.

Forward looking, the current design makes even more sense since we predict that the current E7500 will have only a short lifespan. As soon as the 533 MHz FSB is fully validated, it is conceivable that Intel will implement it not only in the Northwood but, most likely, in the Xeon-based platforms as well. In this case, aside from a few other minor reiterations, the only real changes will concern the phase lock loops (PLLs) and the new E7500-B will be a drop-in replacement for the current revision.

I7500 Chipset Interconnectivity
(picture courtesy of Intel)

The four I/O interfaces constitute three point to point Hub Interface 2.0 connections (HubLink; HL) with a bandwidth of 1066 MB/sec each, utilizing a 16 bit interconnect running at 266 MB data rate and one HL 1.5 interface to the ICH 3-S at 8 bits width and 133 MHz for a peak bandwidth of 266 MB/sec. Each P64H2 contains two independent 64-bit PCI-X interfaces and two PCI hot plug controllers, one per PCI-X interface. Each 64-bit PCI-X segment supports multiple PCI-X slots for high-bandwidth connectivity of next-generation components such as Gigabit Ethernet adapters and I/O processors

The ICH3-S is an evolution of the know ICH and ICH2 and provides legacy I/O interfaces through integrated features including a two-channel Ultra ATA/100 bus master IDE controller and three USB controllers for up to six USB ports. The ICH3-S also offers an integrated System Manageability Bus 2.0 (SMBus 2.0) controller, an integrated LAN controller, as well as AC97 2.2-compliant and PCI 2.2-compliant interfaces.

Intel E7500-based board as shown in a Mitac 1U Server featuring 6 DIMM slots for a total of 12 GB Registered Low Profile DIMMs

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