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| ASUS V9280 A Case Study of AGP 3.0 | |
| (Review by MS, Dec. 9, 2002) |
Changes in Pinout
One thing should be clear, it is not possible to ensure progress and at the same time backward compatibility without proper identification of the changes on the hardware level. This identification requires specific signals that, if they were not provided for earlier, have to be added in form of extra pins. The addition of extra physical pins, however, would negate backward compatibility since it would require a change in the physical layout of the interface. As a prophylactic countermeasure for situations like this, most interfaces are introduced with a number of no-connect or don't care pins that can be used at later time to add extra features.
The transition from AGP2.0 to AGP3.0 encompasses the activation / recruitment of four of these "Sleepers" and the redefinition of two other pins. Technically, it is a 3+3 change since one of the new pins is "borrowed from the former PIPE signalling command bus but since the PIPE scheme is discontinued entirely, the remapping qualifies as a new pin.

Backside of the AGP interface electrical interface of the V9280S (AGP 3.0). All pins are there.

Backside of the AGP interface electrical interface of the ASUS V8460 (Ti 4600; AGP 2.0). Note the missing pins. On many AGP 2.0 graphics adapters the missing pins are actually present, however, in those cases, they are simply no-connects, that is without any function. The missing pins of interest are the ones pointed out by the black arrows, that is pins A3 (GC_DET#) and A11 (MB_DET#) which signal whether the graphics card and mainboard are AGP 3.0 capable or not.
Briefly, the complete listing of pinout changes is:
| Signal | Pin# | Type | Description |
| AGP_Vrefcg | B66 | static | mainboard to graphics card reference voltage |
| AGP_Vrefgc | A66 | static | graphics card to mainboard reference voltage |
| GC_DET# | A3 | static | forces AGP 3.0 mode on graphics card |
| MB_DET# | A11 | static | forces AGP 3.0 mode on mainboard |
| DBI_HI | A12 | source synchronous | DBI upper block (AD[31:16]) |
| DBI_LO | B14 | source synchronous | DBI lower block (AD[15:00]) |
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