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LOSTCIRCUITS

SHORTCUTS:
RADEON 9000Pro
R300 At One Glance
Transistors, Power, Quad Memory Controller
AGP X8, Vertex Shaders
HYPER Z III
Floating Poing Pixel Engines
Dyanmics of Light and Pipelines
Bump mapping instead of modeling
Anti Aliasing
Hairy Edges
Multiple Render Targets, Monkeys and Epitaph

Hot Offers for the FireGL

 ATI RADEON 9000 / 9700
No Paper Tigers
(Review by MS, July 20, 2002)

Z Occlusion Culling

The major hog of bandwidth with conventional graphics cards has been what is called pixel overdraw. Behind this term, as our loyal readers will know (as well as the loyal readers of other websites) hides the fact that a triangle setup engine is not capable of making intelligent choices of whether any given pixel will be visible or hidden behind another object in the same scene. The net result is that up to 300% more pixels than what is actually visible have to be rendered in any given scene, which means an Overdraw of 300%. This naturally means a huge waste of bandwidth on invisible pixels. Elimination of pixel overdraw by means of tile-based architecture was what make PowerVR and their Kyro(II) cores famous. There are different ways of defurring a feline, though, and ATi has been very actively involved in these features since the R100 days. What we are looking at today is called HYPER Z-III architecture and uses the following steps:


I. Hierarchical Z

Hierachical Z occlusion culling (eliminating blocks of pixels) hidden behind any other triangle. This is the easiest and earliest step in eliminating overdraw but it only catches pixels inside a triangle whereas edge pixels are still subject to overdraw.

II. Early Z

Early Z: Early Z is essentially a refinement of HierarchicalZ and screens data down to the pixel level to eliminate invisible pixels before they reach the pipeline. With higher polygon counts, the triangles themselves become smaller and smaller, thus, the number of edge pixels gets larger and refining the occlusion culling to the pixel level will remove increasingly more pixels compared to the Hierarchical Z technique. Add the advanced complexity of pixel shading algorithms, and the early elimination of invisible pixels gains tremendous impact with respect to saving bandwith and computing power.

III. Fast Clear III

The latest implementation of Fast Clear is basically an evolution of the earlier versions and uses the same trick of simply tagging pixels with a "dirty flag" in the tag cache instead of clearing the z-buffer. In plain English, what that means is that there is a tagRAM cache that can be used to flag every scene on a pixel by pixel basis. Only pixels that have been flagged as dirty need to be updated and instead of clearing the z-buffer and then writing new data to it, the existing data are declared either valid or dirty and simply updated as needed instead of erasing the z-buffer first and then writing a new set of data to it. This technique eliminates 63/64 of memory bandwidth to the z-buffer compared to the conventional clear and rewrite technique. The main improvement over earlier Fast-Clear version is that the tag register size has increased to eliminate the 1024 x 768 pixel resolution limitation of earlier RADEON cores for the use of Fast Clear.

IV. Compression

New lossless compression algorithms are used to compress data by a factor of 6. In other words, the old S3TC (S3 Texture Compression) is taken to new heights.

Next Page:    => Floating Point Pixel Pipelines =>

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