LOSTCIRCUITS

X800 Architecture

All cores of the X800 family feature 16 pixel pipelines that are capable of carrying out 1536 instructions per pass. In addition, each pixel pipeline features the F-buffer to loop instructions without the need for writing any data back to the local frame buffer, which allows basically unlimited number of instructions in back-to-back multipass processing sequences if they are needed.

Floorplan of the R420 core

The pixel pipes are organized into four blocks of four pipelines, which allows selective enabling / disabling of individual blocks of four for a scalable architecture of four to 16 pixel pipes, depending on yields. A similar situation occurred with the release of the RADEON 9700 and the 9500 with the latter essentially being the same card with four of the eight pipes being disabled. This scalable architecture, in which it does not matter which ones of the four pipelines are enabled or disabled essentially translates into 100% yield on the graphics cores, in case one of the four blocks is dysfunctional, it can be disabled and serve in the RADEON X800 Pro, in case two blocks are problematic, we might see another scaled down version in the future.

Floorplan of the R420 core

Overall, the prospected performance of the X800 core is impressive. The massive parallelism of the core allows up to 80 concurrent shader operations per clock with roughly 192 GigaFLOPs and a fill rate of more than 8.8 Gigapixels / second.

A Word on GDDR III

One of the latest achievements in the graphics card industry is the transition from DDR to GDDR III. Originally it was planned to move from DDR to DDR II, however, the high power consumption and heat dissipation of DDR II combined with the frequency cap of DDR II caused a quick demise of the new memory solution. In short, the advantages of DDR II based on a lower core clock and on-die termination (ODT) did not really yield the expected performance. First of all, ODT is implemented only on the I/Os whereas the command and address bus does not have it in DDR II. This allows frequency scaling of the data bus but the command and addresses abide by the same limitations as in standard DDR. The addition of ODT for address and command allows GDDR3 to run at much higher frequencies.

Another bottleneck of DDR II is the strobing scheme, in that there is a single strobe only for reads and writes. Since writes usually come a bit early and reads are a bit delayed relative to the strobe, this is a one size fits all solution that is not optimal for either data transfer. DDR III and by extension GDDR III solve this problem by separating read and write strobes. On the controller level, the situation is also much simplified in GDDR III in that the output sequence of the four bits per prefetch is now fixed, whereas DDR II allows multiple sequences of the burst. All of these improvements make DDR III a much more viable solution than DDR II.

The memory architecture of the RADEON X800 features four different memory controllers, each serving a 64 bit interface in crossbar configuration which means that each sub controller can access each part of the memory array. According to what we learned from ATI during our briefing, the memory interface further features a dedicated internal cache for each of the memory controllers.

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