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specs
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 Matrox G400 32 MB
Award or no award, that is here the question
(Review by MS; Sept. 16, 1999)

Possible Handicaps

The best video card, no matter how powerful its internal bus design and processor are, must choke if the system logic is unable to provide the necessary data. A variety of reasons can be held accountable for bad performance:

AGP x 4 and hierarchic SRA

Let’s look at reason #2, the AGP interface. The PCI interface is capable of a throughput of 32bit = 4 Bytes per cycle. Running at 33 MHz, therefore, the maximum traffic of data cannot exceed 133 MByte per second. The AGP interface offers 64 bit depth and runs at 66 MHz (under standard conditions) and thus the maximum throughput is increased to 500 Mbytes per second (in AGP x 2 mode). Future chipsets starting with the VIA 694X and the Intel Camino (820) as well as the upcoming VIA KX133 (Slot A) are capable of running in AGP x 4 mode with a maximum throughput of 1GByte/sec.


The key benefit is not only that rendered data from the CPU can reach the graphics chip more effectively but, more importantly, that the local video memory (frame buffer) loses some of its importance. There are several terms that have been created for this scenario, starting from Intel’s unified memory architecture (UMA) to the latest Matrox creation: Symmetric rendering architecture (SRA). What it all comes down to is that the entire system memory (RAM) is treated exactly the same way as the local on-board video memory. In other words, we have direct memory access (DMA) of the graphics chip to any data in the main RAM, as well as direct memory execution (DiME) and therefore, the G400 can draw to, render to and read from the main memory at a transfer rate of 1GByte per second. Moreover, SRA can operate in parallel with access of the local frame buffer, thus providing basically unlimited data access for the graphics engines.

Different memory sections within a PC operate at different speed and historically, local video memory is faster than the system RAM. Therefore, notwithstanding the SRA, a certain hierarchy has been established in that the local frame buffer is given priority over the system RAM to warrant the very best of both worlds. The highest priority, however, is given to data in the large on-chip cache and, thus, the entire G400 graphics subsystem operates in a fashion very similar to the Socket7 architecture with the L1 cache (on-chip), the LFB (comparable to the L2) on board, and a fast system memory interface. As a result, command data, vertex data and texture data in different areas of the memory subsystem can be fetched by the graphics engine in a multithreaded, fully bus mastered way.

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